Microcomputer debug architecture and method

Details Microcomputer debug architecture and method Microcomputer debug architecture and method

1999-10-01

2003-04-29

Beausoliel, Robert (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S031000, C714S047300, C717S124000, C717S129000, C717S131000

Reexamination Certificate

active

06557119

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to microcomputers. More particularly, the present invention relates to methods and apparatus for carrying out debugging operations on microcomputers.
2. Discussion of the Related Art
System-on-chip devices (SOCs), generally microcomputers, are well-known. These devices generally include a processor, one or more modules, bus interfaces, memory devices, and one or more system busses for communicating information. When designing, testing, and checking the microcomputer, it is necessary to operate the microcomputer in a mode so that problems with programs executing on the microcomputer can be identified and corrected. This process of problem identification and correction is known as “debugging”. Because multiple modules and their communications occur internally to the chip, access to this information to this information is generally difficult when problems occur in software or hardware. Thus, debugging on these systems is not straightforward. As a result of development of these SOCs, specialized debugging systems have been developed to monitor performance and trace information on the chip. Such systems typically include dedicated hardware or software such as a debug tool and debug software which accesses a processor through serial communications.
However, debugging an SOC generally involves intrusively monitoring one or more processor registers or memory locations. Accesses to memory locations are sometimes destructive, and data access to a location being read from a debugging tool may impede processor performance. Similarly, accesses are generally performed over a system bus to the processor, memory, or other module, and may reduce available bandwidth over the system bus for performing general operations. Some debugging systems do not perform at the same clock speed as that of the processor, and it may be necessary to slow the performance of the processor to enable use of debugging features such as obtaining trace information. By slowing or pausing the processor, some types of error may not be reproduced, and thus cannot be detected or corrected. Further, accurate information may not be available altogether due to a high speed of the processor; information may be skewed or missing.
Some systems include one or more dedicated functional units within the SOC that are dedicated to debugging the processor, sometimes referred to as a debug unit or module. However, these units affect the operation of the processor when obtaining information such as trace information. These devices typically function at a lower speed than the processor, and thus affect processor operations when they access processor data. The debug system relies upon running debug code on the target processor itself, and this code is usually built into the debugee. Thus, the presence of the debug code is intrusive in terms of memory layout, and instruction stream disruption.
Other debugging systems referred to as in-circuit emulators (ICEs) match on-chip hardware and are connected to it. Thus, on-chip connections are mapped onto the emulator and are accessible on the emulator which is designed specifically for the chip to be tested. However, emulators are prohibitively expensive for some applications because they are specially-developed hardware, and do not successfully match all on-chip speeds or communications. Thus, emulator systems are inadequate. Further, these systems generally transfer information over the system bus, and therefore necessarily impact processor performance. These ICEs generally use a proprietary communication interface that can only interface with external debug equipment from the same manufacturer.
Another technique for troubleshooting includes using a Logic State analyzer (LSA) which is a device connected to pins of the integrated circuit that monitors the state of all off-chip communications. LSA devices are generally expensive devices, and do not allow access to pin information inside the chip.
Conventionally, there are two main types of development system architectures that may be used to debug a microcomputer.
FIG. 1
illustrates a first type of debugging system. The system includes a target processor board
10
. The target processor board
10
has a target processor
12
disposed thereon. Target processor
12
is the microcomputer that is being debugged by the debugging system. A monitor ROM
14
coupled to target processor
12
via data link
16
is also provided. A serial port interface
18
is provide to couple target processor
12
via data link
20
with host computer
22
via data link
24
. Host computer
22
runs a software backplane/operating system
26
that allows a software debugger system
28
to access target processor
12
. In the system illustrated in
FIG. 1
, the target processor
12
may have minimal or no debug features. Most of the tools necessary for debugging the operation of target processor
12
are contained in debugger software system
28
.
The system of
FIG. 1
is somewhat limited in the types of debugging operations that can be performed. Since a serial port is used to communicate between the target processor
12
and the host computer
22
, the system is typically not capable of controlling the CPU directly to, for example, cause target processor
12
to boot from software executing on host computer
22
. In addition, the debugging system of
FIG. 1
can be intrusive since the system relies upon executing code on the target processor
12
itself. Thus, host computer
22
can and does actually disrupt the execution of code on target processor
12
. Since the host computer
22
actually perturbs operation of target processor
12
during debugging operations, the results of the debugging operations may be subject to some uncertainty since the presence of the debugging system itself may alter the behavior of the target processor.
FIG. 2
illustrates another conventional debugging system. In the debugging system of
FIG. 2
, target processor
12
is connected to a debug adaptor
30
via a debug link
32
. A host computer
22
runs a software backplane/operating system
26
that supports debugger system
28
. Host computer
22
communicates with debug adapter
30
via bidirectional data link
34
. Debug adapter
30
is “intelligent”. It includes a CPU
36
and a random access memory
38
that execute adapter software to translate between the communication protocol of the debug link
34
and the communication protocol of the data link
34
. Debug data link
34
may be, for example, an Ethernet connection or a PCI bus.
Optionally, external hardware such as a logic analyzer
40
may be provided that can supply a triggering signal to target processor
12
via trigger-in data link
42
and receive a trigger signal from target processor
12
via trigger-out data link
44
.
The debug system of
FIG. 2
does not require additional off-chip hardware, to interface the target processor to the debugging system, as is needed in the system of FIG.
1
. This allows production target processors
12
to be debugged without requiring that they be combined with additional components prior to connection to the debugging system extra components. In addition, enhanced debugging features can be provided because of the inclusion of debug adaptor
30
in the system. However, the debugging system of
FIG. 2
still suffers from at least the limitation of being intrusive in that the debugging software may still perturb operation of target processor
12
.
SUMMARY OF THE INVENTION
According to one aspect of the invention, there is provided a computer system comprising at least one central processing unit, a memory unit coupled to the at least one central processing unit, a set of watchpoints defined in the computer system, each watchpoint in the set of watchpoints comprising a programmable precondition register that stores a set of precondition codes, wherein the set of precondition codes is identical for each watchpoint in the set of watchpoints, a programmable action register that stores a set of act

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