Microcomputer capable of suppressing power consumption even if a

Details Microcomputer capable of suppressing power consumption even if a Microcomputer capable of suppressing power consumption even if a

1998-03-31

1999-11-23

Butler, Dennis M.

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Multiple or variable intervals or frequencies

713600, G06F 108

Patent

active

059918896

ABSTRACT:
In a microcomputer including a program memory (1) and a CPU (2) operable in one of high-speed and low-speed modes in which the CPU carries out high-speed and low-speed operations when supplied with high-speed and low-speed clock signals (CKH and CKL), respectively, the program memory includes high-speed and low-speed operation memories (11 and 12) for memorizing high-speed and low-speed mode programs which are read by first and second predetermined address ranges of a program address of a program counter (21) of the CPU and which make the CPU carry out the high-speed and the low-speed operations, respectively. A memory controller (3) produces, when detects the second predetermined address range of the program address, a high-speed operation stop signal for stopping operation of the high-speed operation memory. A clock supplying circuit (4) supplies the CPU with one of the high-speed and the low-speed clock signals that corresponds to one of the high-speed and the low-speed modes. The CPU 2 includes an operation mode setting register (22) for setting a different one of the high-speed and the low-speed modes as an operation mode signal (M). In response to the operation mode signal, the clock supplying circuit supplies the CPU 2 with a different one of the high-speed and the low-speed clock signals.

REFERENCES:
patent: 4862348 (1989-08-01), Nakamura
patent: 5426755 (1995-06-01), Yokouchi et al.
patent: 5483659 (1996-01-01), Yamamura
patent: 5511209 (1996-04-01), Mensch, Jr.

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