Microcomputer capable of preventing writing errors in a non-vola

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability

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714 42, 714 54, 711152, 711155, G06F 130, G06F 1100

Patent

active

059251395

ABSTRACT:
When data are to be written in an EEPROM (1), a CPU (2) sets a flag (12). A voltage booster (13) boosts the power voltage in compliance with the setting of the flag (12). A voltage boost detector (14) detects whether the output of the voltage booster (13) is in voltage boost state. If the output of the voltage booster (13) is not in voltage boost state, a latch (15) is reset and the EEPROM (1) is not permitted to switch to write mode. As a result, it is possible to prevent incorrect data writing in the EEPROM (1) even when the flag (12) has been incorrectly set.

REFERENCES:
patent: 4485456 (1984-11-01), Toyoda
patent: 5097445 (1992-03-01), Yamauchi
patent: 5297119 (1994-03-01), Tonegawa et al.
patent: 5381366 (1995-01-01), Kawauchi et al.
patent: 5530938 (1996-06-01), Akasaka et al.

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