Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1997-03-20
1999-07-20
Auve, Glenn A.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714 42, 714 54, 711152, 711155, G06F 130, G06F 1100
Patent
active
059251395
ABSTRACT:
When data are to be written in an EEPROM (1), a CPU (2) sets a flag (12). A voltage booster (13) boosts the power voltage in compliance with the setting of the flag (12). A voltage boost detector (14) detects whether the output of the voltage booster (13) is in voltage boost state. If the output of the voltage booster (13) is not in voltage boost state, a latch (15) is reset and the EEPROM (1) is not permitted to switch to write mode. As a result, it is possible to prevent incorrect data writing in the EEPROM (1) even when the flag (12) has been incorrectly set.
REFERENCES:
patent: 4485456 (1984-11-01), Toyoda
patent: 5097445 (1992-03-01), Yamauchi
patent: 5297119 (1994-03-01), Tonegawa et al.
patent: 5381366 (1995-01-01), Kawauchi et al.
patent: 5530938 (1996-06-01), Akasaka et al.
Watanabe Toru
Yamada Susumu
Yamasaki Shinichi
Auve Glenn A.
Jean Frantz B.
Sanyo Electric Co,. Ltd.
LandOfFree
Microcomputer capable of preventing writing errors in a non-vola does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Microcomputer capable of preventing writing errors in a non-vola, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microcomputer capable of preventing writing errors in a non-vola will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1318137