Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1998-09-30
2004-03-30
Nguyen, T. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C710S107000, C710S108000, C710S110000, C711S147000, C711S148000, C711S149000, C711S152000, C711S156000, C711S164000
Reexamination Certificate
active
06715049
ABSTRACT:
BACKGROUND
0
F THE INVENTION
1. Field of the Invention
The present invention relates to a microcomputer and an information processing system having a memory whose data is protected from an access from the outside.
2. Description of the Prior Art
A CPU-controlled system has busses to which a CPU (central processing unit), a bus master unit, a memory, a peripheral unit, etc., are connected. Recent processing technology frequently packages a CPU and a memory into a single chip to form a microcomputer.
FIG. 1
shows an example of such a CPU-controlled system. The system includes a microcomputer
103
composed of a CPU
101
and a memory
102
, an external bus master unit
104
, an external memory
105
or a peripheral unit. These elements are connected to one another through a data bus
106
, an address bus
107
, and a control signal line
108
. The CPU
101
or the bus master unit
104
acquires a bus right to drive the buses and signal line.
The external bus master unit
104
will not be allowed to access a specific area in the memory
102
where a program is stored, and is allowed to access an area in the memory
102
where data is stored.
FIG. 2
is a timing chart showing a sequence of acquiring the bus right. The bus right acquisition is realized through a handshake using a bus right request signal/BREQ and a bus right authorization signal/BACK. The bus right is controlled by the CPU
101
. When the external bus master unit
104
needs the bus right, it asserts the signal/BREQ. If the CPU
101
is ready to transfer the bus right, it asserts the signal/BACK. Upon receiving the asserted signal/BACK, the bus master unit
104
acquires the bus right and drives the buses. If the bus right becomes not needed, the bus master unit
104
negates the signal/BREQ. In response to this, the CPU
101
negates the signal/BACK and acquires the bus right. In this way, the memory
102
in the microcomputer
103
is easy to access from the outside.
To secure the safety of data in the memory
102
, it is necessary to restrict read and write accesses from the outside to the memory
102
. Accessing the memory
102
from the outside, however, is very easy.
FIG. 3
explains a simple way of accessing the memory
102
from the outside. An operation clock signal CLOCK is supplied to the microcomputer
103
. At proper timing, a reset signal/RESET is asserted and negated, and the bus right request signal/BREQ is asserted. Then, the memory
102
becomes accessible from the outside.
In this way, an external bus master unit can easily access a memory incorporated in a microcomputer only by acquiring a bus right of address and data buses connected to a CPU of the microcomputer. Then, the external bus master unit can easily read or write data from or to the memory. It is difficult to protect data in the memory from external accesses.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a microcomputer and an information processing system capable of protecting data stored in a memory.
In order to accomplish the object, an aspect of the present invention provides a computer having a memory, a CPU, a register, and a control circuit. The memory is accessible from the outside. The CPU controls a bus right to authorize the use of address and data buses running between the CPU and the memory. The CPU receives a bus right request from the outside, and if the request is acceptable, provides the outside with the bus right. The register holds protected addresses that represent protected areas in the memory where an access from the outside is prohibited. The control circuit compares the protected addresses with a target address of a read or write access made from the outside to the memory after the bus right is given to the outside, and if the target address is within the protected addresses, disables the read or write access.
The protected areas in the memory may store programs and specific data.
Another aspect of the present invention provides a computer having a CPU, a memory accessible from the CPU and the outside, an address bus for transferring an address from one of the CPU and the outside to the memory, a data bus for transferring data between the memory and one of the CPU and the outside, a signal line for transferring a read control signal from one of the CPU and the outside to the memory when reading data from the memory, a signal line for transferring a write control signal from one of the CPU and the outside to the memory when writing data to the memory, an input/output buffer for controlling data input/output between the data bus and the outside in response to an output enable signal, an address decoder for enabling the memory upon receiving an address from the address bus, a gate for setting the memory to a write enabled state in response to the write control signal and a write enable signal, an output control circuit for generating the output enable signal and supplying it to the input/output buffer, and a write control circuit for generating the write enable signal and supplying it to the gate.
Still another aspect of the present invention provides a computer having a CPU, a memory accessible from the CPU and the outside, an address bus for transferring an address from one of the CPU and the outside to the memory, a data bus for transferring data between the memory and one of the CPU and the outside, a signal line for transferring a read control signal from one of the CPU and the outside to the memory when reading data from the memory, an input/output buffer for controlling data input/output between the data bus and the outside in response to an output enable signal, and an output control circuit for generating the output enable signal and supplying it to the input/output buffer.
The output control circuit has a read protect register.
The read protect register holds data for specifying read-protected areas in the memory where a read access from the outside is prohibited.
The output control circuit issues the output enable signal if the CPU has a bus right and uses it to carry out a write access to the memory, or if the outside has the bus right and uses it to carry out a read access to an address of the memory that is out of the read-protected areas.
The output control circuit has a comparator for determining whether or not an accessed address is in the read-protected areas.
Still another aspect of the present invention provides a computer having a CPU, a memory accessible from the CPU and the outside, an address bus for transferring an address from one of the CPU and the outside to the memory, a data bus for transferring data between the memory and one of the CPU and the outside, a signal line for transferring a write control signal from one of the CPU and the outside to the memory when writing data to the memory, a gate for setting the memory to a write enabled state according to an AND of the write control signal and a write enable signal, and a write control circuit for generating the write enable signal and supplying it to the gate.
The write control circuit has a write protect register.
The write protect register holds data for specifying write-protected areas in the memory where a write access from the outside is prohibited.
The write control circuit issues the write enable signal if the outside has a bus right and uses it to carry out a write access to an address of the memory that is out of the write protected areas.
The write control circuit has a comparator for determining whether or not an accessed address is in the write-protected areas.
Still another aspect of the present invention provides an information processing system having a microcomputer and an external bus master unit. The microcomputer consists of a memory accessible from the outside, a CPU for controlling a bus right to authorize the use of address and data buses running between the CPU and the memory, the CPU receiving a bus right request from the outside, and if the request is acceptable, providing the outside with the bus right, a register for holding protected addresses that represent protected areas
Kabushiki Kaisha Toshiba
Nguyen T.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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