Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-11-15
2002-12-10
Baderman, Scott (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S036000, C703S028000
Reexamination Certificate
active
06493833
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a microcomputer including a built-in debugging circuit.
2. Description of the Background Art
FIG. 7
is an explanatory diagram showing memory arrangement of a conventional microcomputer including a built-in ROM. As shown in
FIG. 7
, a memory area is formed by a RAM area
5
and a built-in ROM area
6
, and a starting address A
1
is allocated onto the built-in ROM area
6
. The built-in ROM may be formed by a flash memory or a mask ROM. The starting address A
1
is a start address for a program to be executed in reset cancellation after reset cancellation.
A reset circuit
53
generates a reset vector V
1
indicating the starting address A
1
after reset cancellation.
In the conventional microcomputer including a built-in ROM having the aforementioned structure, the reset circuit
53
generates the reset vector V
1
after reset cancellation, so that the program to be executed in reset cancellation is executed from the starting address A
1
on the built-in ROM area
6
.
Consider the case of evaluating a system including the conventional microcomputer including a built-in ROM having the aforementioned structure with an ICE (in-circuit emulator).
When the built-in ROM is a flash memory, an evaluation program (start address=starting address A
1
) is registered in the built-in ROM area
6
of the flash memory from the ICE through the reset circuit
53
so that the evaluation program is executed from the starting address A
1
on the built-in ROM area
6
after reset cancellation.
If the flash memory accepts no writing for some reason, however, the following operations must be performed under control of the ICE.
After registering the evaluation program in the RAM area
5
of the microcomputer through the debugging circuit
53
, it is necessary to perform debugging interrupt processing by setting the microcomputer in a normal mode and making the microcomputer execute processing from the start address for the evaluation program on the built-in RAM under control of the ICE. Thus, the series of operations by the ICE for forcibly executing the evaluation program under control of the ICE are extremely complicated.
Also when the built-in ROM is a mask ROM accepting no writing, the aforementioned series of operations by the ICE are necessary similarly to the case of the flash memory.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a microcomputer including a built-in storage portion capable of registering an evaluation program from an external evaluation unit comprises a CPU; a debugging circuit performing a support operation for registration of the evaluation program from the external evaluation unit in the storage portion and support operation in execution of the evaluation program, and the debugging circuit is capable of generating a reset vector selection signal indicating an address for executing the evaluation program under control of the external evaluation unit; and a reset circuit generating a reset vector in reset cancellation after execution of a reset operation and making the CPU execute a program to be executed in reset cancellation registered on the storage portion on the basis of the reset vector. The reset circuit decides the reset vector on the basis of the reset vector selection signal.
According to the first aspect, the debugging circuit can generate the reset vector selection signal indicating the address for executing the evaluation program, and the reset circuit decides the reset vector on the basis of the reset vector selection signal.
When registering the evaluation program in the storage portion from the external evaluation unit, therefore, it is possible to make the CPU automatically execute the evaluation program as the program to be executed in reset cancellation by generating the reset vector selection signal indicating the address for executing the evaluation program and thereafter resetting the microcomputer, whereby the evaluation program by the external evaluation unit can be executed through a simple operation also when the evaluation program can be written only in a limited area of the built-in storage portion.
According to a second aspect of the present invention, the external evaluation unit includes an ICE (in-circuit emulator).
According to a third aspect of the present invention, the address for executing the evaluation program includes a start address for the evaluation program, and the reset circuit generates the reset vector indicating starting from the start address to make the CPU execute the evaluation program as the program to be executed in reset cancellation when the reset vector selection signal indicates the start address for the evaluation program.
According to the third aspect, the reset circuit generates the reset vector indicating starting from the start address and makes the CPU execute the evaluation program as the program to be executed in reset cancellation when the reset vector selection signal indicates the start address for the evaluation program, whereby the evaluation program starting from the start address is automatically executed in reset cancellation after registration of the evaluation program.
According to a fourth aspect of the present invention, the storage portion consists of first and second storage areas having different electric characteristics, the evaluation program is registered in the first storage area, and the reset circuit generates a reset vector indicating starting from an address on the second storage area when the reset vector selection signal does not indicate the start address for the evaluation program.
According to a fifth aspect of the present invention, the first storage area includes a RAM area, and the second storage area includes a ROM area.
According to a sixth aspect of the present invention, the ROM area includes a rewritable flash memory area.
According to a seventh aspect of the present invention, the storage portion includes an interrupt register capable of storing an interrupt address, the address for executing the evaluation program includes an address of the interrupt register, the debugging circuit is capable of storing the start address for the evaluation program in the interrupt register as the interrupt address under control of the external evaluation unit, and the reset circuit generates a reset vector indicating interrupt processing starting from the interrupt address to make the CPU execute the evaluation program as the program to be executed in reset cancellation when the reset vector selection signal indicates an address of the interrupt register.
According to the seventh aspect, the reset circuit generates the reset vector indicating interrupt processing starting from the interrupt address to make the CPU execute the evaluation program as the program to be executed in reset cancellation when the reset vector selection signal indicates the address of the interrupt register, whereby interrupt processing starting from the start address for the evaluation program is automatically executed in reset cancellation after registration of the evaluation program.
According to an eighth aspect of the present invention, the reset vector selection signal includes a reset address selection signal capable of specifying all addresses on the storage portion.
According to the eighth aspect, the reset vector selection signal includes the reset address selection signal capable of indicating all addresses on the storage portion, whereby the evaluation program can be registered in an arbitrary area on the registerable storage portion.
According to a ninth aspect of the present invention, the reset address selection signal is propagated to the reset circuit through a plurality of signal lines, and the plurality of signal lines are capable of propagating multilevel information allowing recognition of at least three levels, and the reset circuit includes a multilevel determination circuit capable of determining multilevel information of each of the plurality of signal lines.
Accor
Baderman Scott
Lohn John
Mitsubishi Denki & Kabushiki Kaisha
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