Electrical computers and digital processing systems: processing – Instruction alignment
Patent
1997-03-10
1999-10-19
Treat, William M.
Electrical computers and digital processing systems: processing
Instruction alignment
712210, 712212, 712213, G06F 930
Patent
active
059681632
ABSTRACT:
An instruction scanning unit for a superscalar microprocessor is disclosed. The instruction scanning unit processes start, end, and functional byte information (or predecode data) associated with a plurality of contiguous instruction bytes. The processing of start byte information and end byte information is performed independently and in parallel, and the instruction scanning unit produces a plurality of scan values which identify valid instructions within the plurality of contiguous instruction bytes. Additionally, the instruction scanning unit is scaleable. Multiple instruction scanning units may be operated in parallel to process a larger plurality of contiguous instruction bytes. Furthermore, the instruction scanning unit detects error conditions in the predecode data in parallel with scanning to locate instructions. Moreover, in parallel with the error checking and scanning to locate instructions, MROM instructions are located for dispatch to an MROM unit.
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Narayan Rammohan
Southard Shane A.
Tran Thang M.
Advanced Micro Devices , Inc.
Kivlin B. Noel
Merkel Lawrence J.
Treat William M.
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