Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
1999-07-23
2001-05-08
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C257S678000
Reexamination Certificate
active
06228675
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
The present application contains subject matter related to a concurrently filed U.S. Patent Application by Richard C. Ruby, Tracy E. Bell, Frank S. Geefay, and Yogesh M. Desai entitled “MICROCAP WAFER-LEVEL PACKAGE”. This application is being filed contemporaneously herewith, is identified by docket number 10990686-1, and is hereby incorporated by reference.
1. Technical Field
The present invention relates to wafer-level packaging techniques, and more specifically to wafer-level, chip-scale packaging of micro devices.
2. Background Art
In the past, a number of wafer-to-wafer bonding techniques have been developed for packaging micro devices. The techniques have included silicon-to-glass anodic bonding, silicon to silicon fusion bonding, and wafer to wafer bonding using various intermediate materials as the actual bonding media. The connection to a hermetically sealed micro device was generally made either under the bonding media against one of the wafers or through the wafer with grommet-type seals around wire conductors.
In both situations, irregularities would occur around the connection such that a reliable hermetic seal of the wafer package could not be assured.
A relatively simple process that would provide a non-electrical, low temperature method for hermetically packaging micro devices has long been sought. Ideally, all seals would be formed by bonding planar surfaces to planar surfaces with no seals that are penetrated by wire conductors. Also, the ideal included processes that would use standard, or close to standard, procedures available in a chemical semiconductor laboratory or manufacturing facility.
One example of such packaging method is shown in U.S. Pat. No. 5,448,014 to Kong et al. However, Kong et al. requires multi-layer standoffs to adjust the distance between the two wafers. Additionally, the disclosed use of different materials for each of the wafers can cause potentially adverse consequences due to the different thermal coefficients of expansion of the materials when the package is manufactured using heat as disclosed. Further, Kong et al uses metallic conductive vias incorporating gallium and/or mercury, which require barriers to diffusion.
In the past, making electrical contact to the packaged devices was difficult because existing methods did not provide a wafer-to-wafer seal that allowed the electrical conductor to pass through the wafer package itself without the use of grommets or sealing rings in the holes around the wires. The previous sealing rings, besides being very small and difficult to handle, were subject to leaking because of the flexing of the wire conductors in the seal that would open the seal.
Further, with the miniaturization of micro device utilizing systems, small wafer-level packages have become highly desirable. This has meant that ultra-thin, or microcap wafer packages with through contacts, have become the goal for the micro device industry.
Thus, the ability to connect to the micro device inside of a wafer-level package has been a significant problem for many years.
DISCLOSURE OF THE INVENTION
The present invention provides a microcap wafer-level package in which a micro device is connected to bonding pads on a base wafer. A peripheral pad on the base wafer encompasses the bonding pads and the micro device. A cap wafer is processed to form wells of a predetermined depth in the cap wafer. A conductive material is made integral with the walls of the wells in the cap wafer. The cap wafer has contacts and a peripheral gasket formed thereon where the contacts are capable of being aligned with the bonding pads on the base wafer, and the gasket matches the peripheral pad on the base wafer. The cap wafer is then placed over the base wafer so as to bond the contact and gasket to the pads and form a hermetically sealed volume within the peripheral gasket. The cap wafer is thinned to form a “microcap”. Essentially, the microcap is thinned below the predetermined depth until the conductive material is exposed to form conductive vias through the cap wafer to outside the hermetically sealed volume. This via arrangement assures a reliable, high conductivity, hermetically sealed connection into the wafer-level package. Further, this process permits the wafers to be made thinner than previously practical because it forms the microcap in situ and avoids the handling of the fragile microcap during assembly.
The present invention provides a microcap wafer-level package in which a cap wafer is processed to form wells of a predetermined depth in the cap wafer. A semiconductor dopant is deposited in the wells by gas-source, liquid-source, or solid-source diffusion followed by a layer of semiconductor material. The cap wafer is annealed to diffuse the semiconductor dopant into the walls of the wells and into the layer of semiconductor material. This via arrangement assures a reliable, high conductivity, hermetically-sealed connection into the wafer-level package.
The present invention provides a microcap wafer-level package in which a cap wafer is processed to form an array of closely spaced wells of a predetermined depth in the cap wafer. The wells are filled with or become a conductive semiconductor material. A manufacturing process is then used to thin the cap wafer below the predetermined depth until the wells become conductive vias through the cap wafer. Outside bonding pads are formed on the cap wafer over the array of vias in the configuration of the array in order to reduce the overall resistivity of the contacts and tailor the configuration thereof.
The present invention provides an electrical or mechanical micro device in a wafer-level, chip-scale package that hermetically seals the micro device while providing electrical connection through one of the wafers.
The present invention further provides a device in a wafer-level, chip-scale package that allows an electrical connection to the micro device to be made through the wafer sealing the package itself.
The present invention further provides a wafer-level, chip-scale packaging technique utilizing a low-temperature batch process done at the wafer level which results in a hermetic seal and allows electrical contacts to be made to standard bonding pads on top of a cap wafer.
The present invention further provides a relatively simple process that results in a hermetic seal for micro devices which does not require high voltages or temperatures.
The present invention further provides a method of manufacturing a wafer package utilizing process steps and equipment that are standard or close to standard to the processes and equipment used in a typical semiconductor laboratory or manufacturing facility.
The present invention further provides a method of manufacturing a wafer-level package in which a micro device, such as an integrated circuit, can be in one or both wafers.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5448014 (1995-09-01), Kong et al.
Bell Tracy E.
Desai Yogesh M.
Geefay Frank S.
Ruby Richard C.
Agilent Technologie,s Inc.
Hoang Quoc
Nelms David
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