Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device
Reexamination Certificate
2003-01-08
2004-12-21
McPherson, John A. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Imaging affecting physical property of radiation sensitive...
Making electrical device
C430S316000, C430S317000, C438S671000, C438S699000, C438S700000, C438S706000
Reexamination Certificate
active
06833232
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a micro-pattern forming method for a semiconductor device, in particular, which can form a micro-pattern corresponding to high integration of the semiconductor device.
2. Description of the Prior Art
FIG. 1
is a sectional view illustrating a micro-pattern forming method for a semiconductor device of the related art.
First, a conductive film
20
and a photosensitive film
30
are sequentially formed on a first insulator layer
10
. The photosensitive film
30
is patterned to have a pitch ‘&agr;+&bgr;’, and then the conductive film
20
is locally dry-etched using the photosensitive film
30
as a mask. The dry-etched photosensitive film
30
is removed to form a pattern.
In general, as semiconductors are reduced in size, it is more difficult to obtain a precise pattern size even though investment and endeavor are being devoted in large amounts to the formation of super-micro patterning.
For example, if the pattern pitch is about 0.20 &mgr;m, it is necessary to form a micro-pattern having a spacing of about 0.10 &mgr;m in a line of about 0.10 &mgr;m. Where the pattern pitch is about 0.20 &mgr;m, ArF equipment and a photoresist (PR) are conventionally used in the formation of the pattern.
If the pattern pitch is 0.40 &mgr;m, KrF equipment and a PR for the KrF equipment may be used.
However, with the KrF equipment used for patterning a 0.40 &mgr;m pitch and the PR for the KrF equipment, the conventional micro-pattern forming method has not succeeded in patterning a 0.20 &mgr;m pitch.
SUMMARY OF THE INVENTION
The present invention has been made to solve the foregoing problems, and it is therefore an object of the present invention to provide a micro-pattern forming method for a semiconductor device, by which the micro-pattern corresponding to high integration of a semiconductor device can be formed from two materials having a large difference in dry etching, selectivity so as to save manufacturing cost.
According to an aspect of the invention for realizing the above object, a micro-pattern forming method for a semiconductor device having a pitch size of &agr;+&bgr; comprises the following steps of: sequentially forming first and second insulation films on a semiconductor substrate; forming a photosensitive film in a proper configuration on the second insulation film, the photosensitive film having a second pitch size which is twice the first pitch size of &agr;+&bgr;; dry etching the second insulation film using the photosensitive film as a mask; removing the photosensitive film; forming a third insulation film on an entire surface of the substrate including remaining portions of the second insulation film; forming a fourth insulation film on a resultant structure in portions corresponding to those between the remaining portions of the second insulation film; etching the third and fourth insulation films using a proper formal solution, whereby the third insulation film has a dry etching selectivity of 1 to 1 in respect to the fourth insulation film, to first flatten the forth insulation film until the second insulation film is exposed; etching the third insulation film using the fourth and second insulation films as masks to form a third insulation film pattern; and filling a conductive film into spaces between the second and third insulation films and second flattening the conductive film to form conductive lines having a pitch size of &agr;+&bgr;.
It is preferred that the first flattening step is performed via etchback.
It is preferred that the second flattening step is performed via CMP or etchback.
REFERENCES:
patent: 3998678 (1976-12-01), Fukase et al.
patent: 5844274 (1998-12-01), Tsutsumi
Chacko-Davis Daborah
Dongbu Electronics Co. Ltd.
Keefer Timothy J.
McPherson John A.
Seyfarth Shaw LLP
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