Micro fusible link for semiconductor devices and method of...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S131000, C438S132000, C438S600000, C257S529000, C257S530000

Reexamination Certificate

active

06294453

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to semiconductor devices with heat-fusible elements and, more particularly, to a method of forming heat-fusible elements on integrated circuit (IC) chips.
2. Background Description
Semiconductor fusible links are used for both activating redundancy in memory chips and for programming functions and codes in logic chips. Typical fusible links are large structures blown by heat, e.g. from a laser, or from electrical current passed through the fuse.
A typical laser blown fuse is 1 &mgr;m wide by 8 &mgr;m long. Also, because of the size of the laser spot used to program the fuses, laser blown fuse links must be spaced some distance apart (approximately 10 &mgr;m) and, in some instances, guard structures must be placed between fuses to prevent damage to adjacent fuses.
Typically, state of the art electrically blown fusible links, must not melt at normal operating current/voltage chip conditions to avoid inadvertently blown fuses. So, state of the art electrically programmed fuses require relatively large currents to open the fuse link. Therefore, higher current/voltage levels are supplied, typically, by external sources to program electrically blown fuses.
One way of facilitating melting fuse links is to provide a resistive heat source under the fusible link. See, for example, U.S. Pat. No. 4,814,853 entitled “Semiconductor Device With Programmable Fuse” to Uchida. Uchida teaches placing a fusible link on a thin insulator above a resistive wire. The resistive wire heats the fusible link to near its melting point and current passing through the link opens it. Unfortunately, Uchida requires that two sets of wires be provided to each fusible link, one for the fusible link and the other for the heater. Also, some of the heat generated in the resistive wire is partially thermally insulated by the insulating film which dissipates into the chip below it.
Consequently, state of the art fusible link structures currently use a significant amount of chip surface area. Space is also required to provide clearance for the physical disruption of the link and its surrounding area that may occur when the fusible link is blown. Thus, the area above and around the fusible link must be kept clear. There is a limit to wiring that can occur under the fusible link as well. As circuit density increases and chip sizes decreases, the area occupied by large fusible links remains a problem.
Thus, there is a need for a very small and compact fusible link that uses less chip surface space.
SUMMARY OF THE INVENTION
It is a purpose of the invention to provide an electrically fusible link that is small in size;
It is another purpose of the present invention to allow more and/or denser arrangements of fusible links;
It is yet another purpose of the present invention to reduce the current/voltage required to fuse fusible links.
The present invention is an electrically programmed fuse and the method of manufacture thereof. The preferred fuse structure includes a high melting point heater element in series with a low melting point fusible link. The heater element has a higher resistivity and larger cross-sectional area than the fusible link in order to withstand heat that the heater element generates to bring the fusible link to its melting point, with a thermal mass of the heater element being sufficient to melt the fusible link. The fuse may be formed on or in the surface of an integrated circuit (IC) chip. Preferred fuse dimensions (width and length) are each between 0.1 and 1 micron.


REFERENCES:
patent: 3619725 (1971-11-01), Soden et al.
patent: 3881241 (1975-05-01), Masuda et al.
patent: 4042950 (1977-08-01), Price
patent: 4135295 (1979-01-01), Price
patent: 4198744 (1980-04-01), Nicolay
patent: 4460914 (1984-07-01), te Velde et al.
patent: 4682204 (1987-07-01), Shiozaki et al.
patent: 4796075 (1989-01-01), Whitten
patent: 4814853 (1989-03-01), Uchida
patent: 4873506 (1989-10-01), Gurevich
patent: 5256899 (1993-10-01), Rangappan
patent: 5389814 (1995-02-01), Srikrisnan
patent: 5420455 (1995-05-01), Gilmour et al.
patent: 5444287 (1995-08-01), Bezama et al.
patent: 5585663 (1996-12-01), Bezama et al.
patent: 5618750 (1997-04-01), Fukuhara et al.
patent: 5621375 (1997-04-01), Gurevich
patent: 5625218 (1997-04-01), Yamadera et al.
patent: 5627400 (1997-05-01), Koga
patent: 5963825 (1999-10-01), Lee et al.
IBM Technical Disclosure Bulletin, vol. 29 No. 3 Aug. 1986, pp. 1291-1292.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Micro fusible link for semiconductor devices and method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Micro fusible link for semiconductor devices and method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Micro fusible link for semiconductor devices and method of... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2532855

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.