Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
1999-06-29
2002-01-29
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S102000, C711S154000, C711S170000
Reexamination Certificate
active
06343353
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a micro-controller unit and, more particularly, to a micro-controller unit for accessing external memory having different access time using a microcode.
DESCRIPTION OF THE PRIOR ART
In general, an embedded application is used to control. Once hardware is decided, a method for controlling it is decided and the method is implemented by programs. Accordingly, such program as well as its size is different according to hardware.
A typical micro-controller unit (hereinafter, referred to as MCU) includes an internal memory such as a code memory for storing microcodes and a data memory for storing data. However, the internal memory of MCU alone may not carry out the large-size embedded application. In that case, an additional external memory may be used to carry out the large-size embedded application.
Accordingly, the MCU includes a memory management unit (hereinafter, referred to as MMU) for controlling read/write operations of the external memory and provides an instruction that enables the MCU to access the external memory.
In addition, the MMU of MCU should have flexibility, that is, ability to accessing the various external memory devices having various characteristics, one of which is the access time.
FIG. 1
is a block diagram illustrating a conventional MCU for accessing the external memory using a handshake method. Referring to
FIG. 1
, the MCU includes a data path
10
, a microcode ROM
12
, a MMU
14
and a bus unit
16
. In case of accessing the external memory, the MMU
14
outputs an external memory request signal REQUEST to the bus unit
16
. The bus unit
16
generates a memory access bus cycle signal BUS CYCLE in repose to the signal REQUEST to access the external memory
18
. After accessing the external memory, the bus unit
16
outputs a signal READY to the MMU
14
to inform that it is already ready to send the accessed data and the accessed data are then transmitted to the data path
10
.
In the conventional mechanism to be described above, since the access to the external memory is operated through the MMU
14
and the bus unit
16
, the operation of accessing the external memory is separated from the internal operation of MCU. Therefore, the MCU may have the high flexibility. However, since the additional hardware such as the MMU and the bus unit is needed and the number of microcodes for internal controls is increased, problems may occur in that the size of the circuit becomes larger.
FIGS. 2 and 3
are timing charts illustrating basic read and write cycles of the external memory, respectively.
Referring to
FIGS. 2 and 3
, in order to satisfy a various access time of external memory devices having various read/write cycles, an address latch enable signal ALE, a read enable signal RD# and a write enable signal WR# should appropriately be extended according to the specification of the external memory. Where a Port
1
is used as an address/data sharing bus and a Port
2
is used as an address bus.
Referring to
FIG. 4
, an operation of the conventional MCU using the handshake method will be described in details. An instruction for accessing the external memory is “MOVX” and the instruction is operated according to a microcode.
In case of the MOVX instruction, a microcode program counter
20
for increasing a program counter value one by one generates a signal ACTIVE to a MMU
14
, and then stops increasing the program counter value. When a handshake operation between MMU
14
and the bus unit
16
is completed, the MMU
14
outputs a resuming signal RESUME to the microcode program counter
20
. The microcode program counter
20
restarts to increase the program counter value in response to the resuming signal RESUME and sequentially outputs addresses of a next microcode to the microcode ROM
12
.
Consequently, the MCU operation is simplified by separately processing a complicated function through the MMU and the bus unit. However, when a small-size MCU is used as the embedded controller processing a simple operation, hardware such as the MMU and the bus unit is needless and the total stability may be degraded.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a micro-controller unit for accessing an external memory using a microcode, thereby scaling down the chip size and improving a stability of the circuit.
In accordance with an aspect of the present invention, there is provided the micro-controller unit for accessing an external memory according to the characteristics of the external memory, comprising: a ROM storing a series of codes including sequence, address latch enable, read enable and write enable fields, wherein the ROM outputs one of codes in response to a counting value and a program counting determining means for determining the counting value in response to the sequence field of the outputted code from the ROM and for outputting the counting value to the ROM.
In accordance with another aspect of the present invention, there is provided a micro-controller unit for accessing an external memory according to the characteristics of the external memory, comprising: a) a first storage means for storing microcodes; b) a programmable memory means for storing cycle extension data of a address latch enalbe signal and a wait signal and for selectively outputting the cycle extension data as an offset value to a microcode program counting means in response to a sequence field from the first storage mean; and c) the microcode program counting means for increasing a program counter value in response to the offset value from the programmable memory means and for outputting an increased program counter value to the first storage means when the offset value is received from the programmable memory means.
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Hyundai Electronics Industries Co,. Ltd.
Jacobson & Holman PLLC
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