Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data...
Reexamination Certificate
2007-01-23
2007-01-23
Cao, Chun (Department: 2115)
Electrical computers and digital processing systems: support
Clock control of data processing system, component, or data...
C713S300000, C713S323000
Reexamination Certificate
active
10690574
ABSTRACT:
It is an object to increase a speed of a CPU operation irrespective of an operation speed of a peripheral circuit and to prevent an increase in power consumption from being thereby caused. A clock generating circuit (10) generates two clocks having phases which are equal to each other, that is, a CPU clock (CLKCPU) and a bus clock (CLKBUS). A BIU (bus interface unit) (51) controls a code bus based on the CPU clock (CLKCPU) and controls a peripheral bus based on the bus clock (CLKBUS). The clock generating circuit (10) switches a frequency of each of the CPU clock (CLKCPU) and the bus clock (CLKBUS) depending on an operation mode of an MCU. For example, a speed of the CPU clock (CLKCPU) is set to be higher than that of the bus clock (CLKBUS) in order to carry out a high-speed operation of a CPU. Also in that case, the phases of both clocks are equal to each other. Consequently, the code bus and the peripheral bus in the BIU (51) can easily be controlled.
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Nakamura Kazuo
Takahashi Hiroki
Cao Chun
Renesas Technology Corp.
Tran Vincent
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