Micro controller unit

Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data...

Reexamination Certificate

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C713S300000, C713S323000

Reexamination Certificate

active

10690574

ABSTRACT:
It is an object to increase a speed of a CPU operation irrespective of an operation speed of a peripheral circuit and to prevent an increase in power consumption from being thereby caused. A clock generating circuit (10) generates two clocks having phases which are equal to each other, that is, a CPU clock (CLKCPU) and a bus clock (CLKBUS). A BIU (bus interface unit) (51) controls a code bus based on the CPU clock (CLKCPU) and controls a peripheral bus based on the bus clock (CLKBUS). The clock generating circuit (10) switches a frequency of each of the CPU clock (CLKCPU) and the bus clock (CLKBUS) depending on an operation mode of an MCU. For example, a speed of the CPU clock (CLKCPU) is set to be higher than that of the bus clock (CLKBUS) in order to carry out a high-speed operation of a CPU. Also in that case, the phases of both clocks are equal to each other. Consequently, the code bus and the peripheral bus in the BIU (51) can easily be controlled.

REFERENCES:
patent: 5473768 (1995-12-01), Kimura
patent: 5778237 (1998-07-01), Yamamoto et al.
patent: 5903746 (1999-05-01), Swoboda et al.
patent: 6081143 (2000-06-01), Ho et al.
patent: 6163851 (2000-12-01), Yamazoe et al.
patent: 6268749 (2001-07-01), Fisch et al.
patent: 6895518 (2005-05-01), Wingen
patent: 11-272644 (1999-10-01), None

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