Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
2001-08-17
2004-11-09
Fleming, Fritz (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S028000
Reexamination Certificate
active
06816921
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The technical field of this invention is data transfer and data bus systems within computer systems.
BACKGROUND OF THE INVENTION
As computer systems have grown more complex, it has become common to employ multiple processors and a wide variety of peripheral devices to transfer data within a chip and from the chip to external devices and vice versa. Such systems almost always have a multiple set of busses separating, for convenience and performance reasons, the communication between similar devices. Multiple bus systems must provide bus controllers to allow for coherent and collision-free communication between separate buses. Micro-controllers are used for this purpose and they provide bus arbitration which determines, at a given time, which device has control of the bus in question.
A prominent standard bus system has emerged for high performance micro-controller designs. The ‘Advanced Micro-controller Bus Architecture System’ AMBA has been defined by Advanced RISC Machines (ARM) Ltd. (Cambridge, U.K.) and is described in U.S. Pat. No. 5,740,461, dated Apr. 14, 1998. Computer systems of a CISC variety are complex instruction set computers and have total backward compatibility requirements over all versions. RISC (reduced instruction set computer) systems, by contrast, are designed to have simple instruction sets and maximized efficiency of operation. Complex operations are accomplished in RISC machines as well, but they are achieved by using combinations of simple instructions. The RISC machines of ARM Ltd. forming the AMBA architecture are of primary interest here.
The standard AMBA has two main busses, a high performance AHB bus and a peripheral bus APB of more moderate performance. The AHB bus is the main memory bus and contains RAM and an external memory controller. In this basic system definition, if a high performance peripheral is required that will transfer large amounts of data, this peripheral is also placed on the high performance AHB bus. This decreases system performance, however, because the central processor unit (CPU) cannot have access to memory when the peripheral has control of the bus.
Advanced RISC Machines Ltd (ARM) has proposed an efficient arbitration scheme and split transfers to allow the CPU and the high performance peripheral to share bus time of the single AHB bus. ARM has also proposed use of a second bus for isolation and using a single arbiter. This proposal still allows only one transaction to progress at a given time period.
The micro-controller DMA of this invention is a general-purpose DMA that is applicable to a wide range of applications. Its major use is to facilitate the rapid transfer of data from one memory location to another with minimal or no CPU overhead. While the micro-controller DMA is moving data, it is possible for the CPU to continue to execute instructions from program memory. This will enable a higher performance system, since the micro-controller DMA relives the CPU of simply moving data.
The DMA is generally used for moving data from a peripheral data register (or buffer) into the system-level RAM. It may also transfer data stored in RAM to the peripheral. Since the system RAM also holds the variables representing the peripheral data, once the micro-controller DMA has moved the data from the peripheral to the RAM, the CPU does not need to access the peripheral to get the updated data. This increases performance in two ways:
1. The CPU does not need to do a load and then store of the data. Only a single load from RAM will suffice.
2. It is more cycle efficient to access the system RAM than the peripheral data registers. In the AMBA system, the AHB bus where data RAM is located, is generally a zero-wait pipelined bus. The APB bus, where most of the peripherals are located, generally requires at least two wait states. The DMA controller relieves the CPU of both the wait-states to the APB bus and in the CPU store operation.
In some bus standards, certain components have a fixed address length defined (such as 32-bits for the APB component of the AMBA) while another part will allow multiple address lengths (such as AHB component of AMBA supporting multiple bus sizes). However, the actual word size of the register may be smaller (such as the 8-bit or 16-bit register in a bus defined for 32-bits) than the fixed address length simply by incrementing by the word size of the register will result in an incorrect address because the address length is fixed at a larger size. The DMA controller needs to support both the variable address length such as in the AHB bus and the fixed address length such as in the APB bus.
SUMMARY OF THE INVENTION
In this invention, a micro-controller DMA is described which includes hardware support for a number of unique features including:
1. Single read of the source address at the larger word size, while permitting multiple sub-word sized writes to the target address.
2. Four sets of control bits are provided. Two sets are for the source address including source word size and source increment size. Two sets are for the target address including target word size and target increment size.
3. A byte shifter/register that will shift a full byte at a time to the next lower byte position allows transfer of a larger word (such as a 16-bit or 32-bit sized word) to a destination having a smaller word size (such as 8-bits or 16 bits).
The above features allow the programmer to set both the actual word size of the source and destination locations and allow the programmer to also set the size to increment. On a fixed bus system such as the APB bus this value can be set to the fixed size. On a variable word-sized system, this can be set to be whatever the current peripheral supports. Completely separate software programmable word size and increment size for both the source and the destination addresses is provided. The address increment size is not dependent upon the word size of the transfer.
The user has complete control over how the micro-controller DMA handles the data and how the address is incremented. All the actual work is still done in hardware so no additional software overhead is required. However, the same micro-controller DMA can now be used to transfer data in a system with different bus standards, such as AMBA having AHB and APB, without compromising efficiency, limiting peripheral or bus efficiency, such as by fixing the sizes of the transfer or unduly burdening the CPU to translate word sizes.
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IBM Technical Disclosure Bulletin,Direct Memory Access Controller, vol. 26, No. 10A, Mar. 1, 1984, entire document.
D. Flynn; AMBA:Enabling Reusable On-Chip Designs, IEEE Micro, IEEE Inc., New York, NY, US; vol. 17, No. 4, Jul. 1, 1997, entire document.
Hamakawa Hiromichi
Jahnke Steven R.
Brady III W. James
Fleming Fritz
Marshall, Jr. Robert D.
Martinez David
Telecky , Jr. Frederick J.
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