Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For high frequency device
Reexamination Certificate
2002-05-01
2003-12-23
Clark, Jasmine (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For high frequency device
C257S691000, C257S660000
Reexamination Certificate
active
06667549
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to micromachined circuits, and more particularly to microwave frequency shielded circuit elements utilizing a low-loss dielectric.
BACKGROUND OF THE INVENTION
There are several techniques for implementing filters and resonators based on microelectronics fabrication techniques. The underlying principle of those filters is a dielectric membrane suspended over a substrate, such as a silicon wafer, with a printed circuit of the filter elements lying on top of the membrane. To facilitate the air gap underneath the membrane, the wafer is etched from the back until the membrane is reached. Filter structures usually require shielding for blocking interference and radiation losses and to some degree for protection from environmental hazards. Previously, microstrip and stripline air-dielectric structures have been micromachined using multiple substrates for the resonant elements and for the ground planes necessary to realize these structures. Typically, microstrip implementations of these devices are formed from two wafers wherein one wafer has a membrane containing resonant circuit elements, and possibly some vias or feedthroughs and the other wafer has a ground plane. The ground plane wafer is then electrically connected to the membrane wafer through vias. Stripline implementations have a third wafer to provide an upper ground plane.
The aforementioned vias or feedthroughs provide electrical connection from one plane of a wafer, to its opposing plane. In one implementation, the ground can be passed from the front surface to the back surface of the wafer for the purpose of providing microwave shielding. In this implementation, several vias of this sort are placed in sufficient proximity to one another to minimize the leakage of microwave energy through the regions between these vias. This minimization of leakage occurs because the “waveguide” which would allow energy to couple out, or leak, is of sufficiently small cross-section that the “waveguide” cut-off is below the frequency of interest for the circuit elements enclosed. Note that the vias only minimize this leakage and they do not eliminate it. Only a continuous “wall” of conductor or a very long “cut-off waveguide” could eliminate this leakage. Thus, multiple ground vias surrounding circuit elements are a compromise brought about by the exigencies of the current fabrication approach limitations.
Some implementations of shielded structures employ multiple layers of wafer. As an example, U.S. Pat. No. 5,608,263 by R. F. Draighton and L. P. B. Katehi discloses a multi-wafer circuit providing at least partial shielding based on metallized semiconductor wafers. It is desirable to create a continuous wall of conductor to improve shielding, thus minimize the energy leakage. It is also desirable to reduce the number of wafers needed to implement Q-efficient microwave structures. Thus, it is desirable to provide a microcircuit with a sculpted ground plane and it is to this end that the present invention is directed.
SUMMARY OF THE INVENTION
In accordance with this invention, monolithic dielectric structures are effectively shielded from their immediate surroundings through the implementation of transversely elongated “vias” which form continuous walls that effectively enclose the circuit elements. Further, these walls incorporate a ground plane within this same substrate, which allows for the realization of such structures on a single substrate for microstrip devices, and for realization of stripline structures utilizing only two substrates. This is accomplished without need for attachment to an additional metallized substrate as has been suggested previously. This aspect of the instant invention is called “Sculpted Ground-plane,” or SGP.
A filter structure consists of a metallized printed circuit on a membrane, wherein the membrane is suspended over a cavity and a sculpted metal ground plane. The cavity is either filled with a dielectric, which can be the original substrate or can be a filled-in dielectric material, or the cavity is not filled which leaves the membrane suspended over air and the SGP. An alternate structure consists of a metallized printed circuit on a dielectric layer that fills a cavity in the substrate, wherein the cavity lays above a SGP. The edges of the SGP are exposed at the topside, providing continuous ground connection between the SGP and the topside metallization.
In accordance with the invention, a process is available for producing a filter structure with a sculpted ground plane. The process starts with a flat substrate material, such as a silicon wafer, which is selectively etched from the bottom side to create a recessed plane. A dielectric membrane is deposited on top and then the wafer is further etched selectively from the back until via sections form underneath the membrane. The backside is then metallized and the membrane is selectively etched. A metallization layer following the filter and side ground planes is deposited on top using plating and lithography processes, wherein some of the metal creates a continuous bond with the back side metal, thus acting as elongated via holes.
The above process may include additional steps for improved-high-frequency performance. One additional set of process steps eliminates the substrate material locked between the membrane and the SGP. After completing the previous process, holes are etched onto the membrane and the substrate underneath the membrane is etched out, leaving an air-suspended membrane. Another alternative set of process steps leaves the membrane with a dielectric layer underneath. In this alternative set of process steps, a wafer is selectively etched from the top to leave a gap at the depth of the recessed plane and elongated vias. The wafer is then filled with the dielectric material and the wafer top is flattened until the metal vias are exposed. The wafer top is then selectively metallized with the filter and top ground plane pattern. More process variations and the details of the above structures and processes are discussed in the description below.
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Bridgewave Communications, Inc.
Clark Jasmine
Gray Cary Ware & Freidenrich
Lohse Timothy W.
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