Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With semiconductor element forming part
Reexamination Certificate
2002-05-29
2003-11-18
Clark, Jasmine (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With semiconductor element forming part
C257S684000, C257S670000, C257S783000, C257S787000
Reexamination Certificate
active
06650005
ABSTRACT:
FIELD OF THE INVENTION
The present invention is relating to an integrated circuit package, particularly to an integrated circuit package with micro BGA configuration.
BACKGROUND OF THE INVENTION
In the integrated circuit packaging industry, it is a trend that a lead frame being as a die carrier has been displaced by a wiring substrate, such as BGA substrate (Ball Grid Array substrate) that generally is to adhere a die on a surface of BGA substrate and to bond solder balls on another surface of wiring substrate for surface mounting.
An integrated circuit package with micro BGA configuration is disclosed in U.S. Pat. No. 5,776,796 “method of encapsulating a semiconductor package”. As shown in
FIG. 1
, a semiconductor die package
10
comprises a semiconductor die
12
and a die carrier
14
. The die carrier
14
is composed of a dielectric layer
16
and a spacer layer
20
with elasticity. A plurality of leads
22
electrically connect the semiconductor die
12
with the dielectric layer
16
of die carrier
14
made from a thin sheet of polyimide, so that the semiconductor die
12
can electrically connect to the terminals
26
on the top surface
18
of the die carrier
14
. The semiconductor package
10
is set in a frame
42
, a cover
30
is attached below the frame
42
, and the cover
30
attaches the top surface
18
of die carrier
14
for protecting the terminal
26
during encapsulating. Next, the introduction of package body
40
may carry out by using needle-like dispenser
32
. Comparing naturally potting method with molding technique, the leads
22
form many tiny apertures between die
12
and dielectric layer
16
so that gas bubbles are easy to be formed, otherwise a vacuum laminating is necessary. Moreover, the shape of solidified package body
40
has no mechanically fastening function but adhesive function against the die carrier
14
. Moisture will permeates into the interface between the package body
40
and the dielectric layer
16
. The bonding strength between semiconductor die
12
and die carrier
14
becomes weaker resulting in delamination or popcorn easily.
SUMMARY
A first object of the present invention is to provide an integrated circuit package with excellent bonding strength between wiring board and chip without delamination happen. A package body has a fastener extending around the lateral surfaces of the wiring board to hold wiring board.
A second object of the present invention is to provide an integrated circuit package, which comprises a wiring board having support bars. The support bars allow an extending fastener of package body to be formed around the lateral surfaces of wiring board for forming a well-bonded package body by molding method. The extending fastener prevents moisture from penetrating into the lateral surfaces of wiring board.
In accordance with the integrated circuit package of the present invention, it comprises a wiring board having a die-attaching surface, a surface-mounting surface and lateral surfaces between the die-attaching surface and the surface-mounting surface. Preferably, the wiring board has a plurality of support bars for supporting the wiring board during molding. A die having a plurality of bonding pads is adhered on the die-attaching surface of wiring board. The bonding pads of die are electrically connected with the wiring board by a plurality of metal bonding wires. A package body formed by molding seals the metal bonding wires and has an extending fastener around the lateral surfaces of the wiring board for holding the wiring board.
REFERENCES:
patent: 5420460 (1995-05-01), Massingill
patent: 5776796 (1998-07-01), Distefano et al.
patent: 5844168 (1998-12-01), Schueller et al.
patent: 6013946 (2000-01-01), Lee et al.
patent: 6218731 (2001-04-01), Huang et al.
patent: 6252298 (2001-06-01), Lee et al.
patent: 6320267 (2001-11-01), Yukawa
Hung Chia-Yu
Lai Chien-Hung
Su Chun-Jen
Clark Jasmine
Troxell Law Office PLLC
Walsin Advanced Electronics LTD
LandOfFree
Micro BGA package does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Micro BGA package, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Micro BGA package will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3175913