Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2000-03-28
2001-12-11
Clark, Jhihan B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S692000, C257S690000, C257S694000, C257S696000, C257S666000
Reexamination Certificate
active
06329708
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a micro Ball Grid Array (&mgr;BGA) semiconductor device.
This application is a counterpart application of Japanese application Serial Number 117442/1999, filed Apr. 26, 1999, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
FIG. 1
is a cross-sectional view of a conventional &mgr;BGA semiconductor device. The conventional &mgr;BGA semiconductor device
1300
is made up of a semiconductor chip
1301
, conductive layers or strips
1310
and a tape
1308
. An integrated circuit having a plurality of external terminals
1304
is formed on a front or top surface of the semiconductor chip
1301
. The tape
1308
includes insulating layers
1309
,
1313
with the conductive layers which are sandwiched between the insulating layers
1309
,
1313
. For example, the conductive layer
1310
is made of copper (Cu). The insulating layer
1309
is made of polyimide or glass epoxy, while the insulating layer
1313
is made of solder resist.
A passivation layer
1305
covers the front surface of the semiconductor chip
1301
. Each of the conductive layers
1310
is electrically connected to one of the plurality of external terminals
1304
and is exposed from an opening portion (hereinafter referred to as an “opening”)
1303
a
. The tape
1308
is fixed to the passivation layer
1305
via a buffer layer
1307
. The connection portions of the conductive layers
1310
to the external terminals
1304
are covered by a resin
1302
.
The conventional &mgr;BGA semiconductor device, however, can not be stacked and mounted on the board, since the exposed regions of the conductive layers
1310
from the openings
1303
a
, which are used for electrical connection with the other external device such as a semiconductor device, are formed only on the front side of the semiconductor chip
1301
.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor device and a semiconductor module which can be stacked and mounted quite readily.
To achieve the object, according to one aspect of the present invention, there is provided a semiconductor device, which is made up of a semiconductor chip including an integrated circuit (not shown) having a plurality of external terminals, the integrated circuit being formed on a front surface of the semiconductor chip; and a tape extending from the front surface to a back or bottom surface of the semiconductor chip and being fixed to the semiconductor chip on the front and the back sides of the semiconductor chip; wherein the tape includes insulating layers and a plurality of conductive layers that are sandwiched between the insulating layers, each of the plurality of conductive layers is electrically connected to one of the plurality of external terminals, and the plurality of conductive layers are exposed from opening portions of the insulating layer at the front side and the back side of the semiconductor chip.
According to another aspect of the present invention, there is provided a semiconductor module, which is made up of a first semiconductor device having a semiconductor chip including an integrated circuit with a plurality of external terminals, the integrated circuit being formed on a front surface of the semiconductor chip; and a tape extending from the front surface to a back surface of the semiconductor chip and being fixed to the semiconductor chip on the front and the back sides of the semiconductor chip; wherein the tape includes insulating layers and a plurality of conductive layers that are sandwiched between the insulating layers, each of the plurality of conductive layers is electrically connected to one of the plurality of external terminals, and the plurality of conductive layers are exposed from opening portions of the insulating layer at the front side and the back side of the semiconductor chip; and a second semiconductor device being electrically connected to the exposed conductive layers from the opening portions.
REFERENCES:
patent: 5714405 (1998-02-01), Tsubosaki et al.
patent: 5805422 (1998-09-01), Otake et al.
patent: 5895970 (1999-04-01), Miyoshi
patent: 6002167 (1999-12-01), Hatano et al.
patent: 6165817 (2000-12-01), Akram et al.
Clark Jhihan B
Oki Electric Industry Co. Ltd.
Rabin & Berdo P.C.
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