Semiconductor device manufacturing: process – Chemical etching – Having liquid and vapor etching steps
Reexamination Certificate
1999-06-01
2001-08-21
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Having liquid and vapor etching steps
C438S706000, C438S723000, C438S724000, C438S745000, C438S756000, C438S757000
Reexamination Certificate
active
06277757
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an improved method, which involves a “wet-by-dry” process (which may also be called a simultaneous “wet-and-dry” process), for making vias in a semiconductor device that are typically formed to connect two conducting layers that separated by a dielectric layer. More specifically, the present invention relates to an improved wet-by-dry etching process (i.e., using simultaneous wet and dry etching processes) for making funnel-shaped (i.e., a tapered or bowl-shaped section above a straight section) vias in a semiconductor device. The present invention also relates to the improved vias fabricated from the novel process of so disclosed. One of the main advantages of the present invention is that vias can be made to have a smooth profile, and that the sharp angles that are typically present between the via and the photoresist and between the wet and dry etched regions, can be substantially ameliorated. Another main advantage of the present invention is that the improved vias can be fabricated without substantially increasing the manufacturing cost or unduly complicating the manufacturing process.
BACKGROUND OF THE INVENTION
In the fabrication of ultra-large-scale integrated (ULSI) circuits, vertical stacking, or integration, of a plurality of metal wiring circuits, or metal layers, to form a multilevel structure has become an efficient way to improve circuit performance and increase the functional complexity of the circuits. The metal wiring circuits are connected by the so-called “vias”, which are formed through a dielectric layer sandwiched by two adjacent metal layers.
Vias are formed typically by first forming through holes in the dielectric layer, followed by the deposition of a conductive material into the through holes. In order to improve the step coverage of a subsequent deposition process, especially a sputter deposition process, in the through hole that has been formed in a dielectric layer on top of a conductive layer, the through hole is often formed to have a funnel shape, i.e., a generally straight lower portion and a tapered portion radiating from the mouth of the straight lower portion. Such a funnel shaped through hole is typically formed using a so-called wet-by-dry etch process, by which the dielectric layer is etched using, simultaneously, a wet etch process and a dry etch process. The dry etch process, which is substantially anisotropic, forms a straight passageway in the dielectric layer. The wet etch process, which is substantially isotropic, causing the passageway to be widened in the direction substantially perpendicular to the dry etching direction. As the dry etch progresses, the extent of wet etch accumulates, and the accumulated extent of the wet etch decreases with increased depth into the dielectric, due to decreased wet etch time. Thus, the final result is a funnel shaped via (i.e., through hole) consisting of two sections, a dry etch (i.e., lower) section with a generally uniform width, and a wet etch (i.e., upper) section with a tapered or bowl-shaped width. The width of the wet etch upper section increases from the mouth (i.e., the intersection between the dry etch lower section and the wet etch upper section) to the top surface of the dielectric layer.
One of the disadvantages of the funnel-shaped vias formed with the conventional wet-by-dry process is that the tapered section has a very steep curve-up portion. This can substantially reduce the step coverage efficiency that the funnel-shaped vias are intended to provide. To maximize the step coverage efficiency in a subsequent sputter depositing process, the tapered section should be as smooth as possible, and the steep curve-up portion near the top of the via should be substantially reduced.
Another disadvantage of the funnel-shaped vias formed with the conventional wet-by-dry process is that there exist sharp angles between the dry etch section and the wet etch section, and between the via and the photoresist (which is the also the exit angle of the via at the top dielectric surface). The sharp exit angle is also related to the steep curve-up portion of the tapered section of the via discussed above. These sharp angles can cause some blind spots in the overall fabrication process and result in reduced production yield.
Due to the high degree of competition in the semiconductor industry, it is important to take careful looks at every possible way that may improve production yield. Preferably, such improvement is done in a cost-effective manner.
SUMMARY OF THE INVENTION
The primary object of the present invention is to develop a method to fabricate vias in semiconductor devices with improved profile. More specifically, the primary object of the present invention is to develop a method to fabricate vias with a smoothen tapered section so as to achieve most efficient step coverage in a subsequent sputtering process to fill the via with a conductive material. The vias fabricated using the process of the present invention also eliminate the sharp angles between the wet etch section and the photoresist, and between the wet etch section and the dry etch section.
The method disclosed in the present invention can be summarized as comprising the following main steps:
1. Depositing a bottom dielectric layer on a wafer, the bottom dielectric layer has a first predetermined etch removal rate;
2. Depositing at least one profile modifying dielectric layer on the bottom dielectric layer;
3. Depositing a top dielectric layer on top of the at least one profile modifying dielectric layer, the top dielectric layer has a second predetermined etch removal rate, wherein the second predetermined etch removal rate is higher than the first predetermined etch removal rate;
4. Forming a photoresist layer on the top dielectric layer, the photoresist layer containing an opening so as to allow a via to be formed through the multiplicity of the dielectric layers;
5. Using a simultaneous wet-and-dry etching process to form a funnel-shaped via in the multiplicity of dielectric layers.
Prior to the deposition of the bottom dielectric layer, a base dielectric layer is deposited on the wafer. Generally, the simultaneous wet-and-dry etching process is conducted such that the straight section of the funnel-shaped via is formed in the base dielectric layer, and the tapered section of the funnel-shaped via is formed in the multiplicity of dielectric layers. However, the straight section of the funnel-shaped via can be formed partially into the multiplicity of dielectric layers, and, likewise, the tapered section of the funnel-shaped via can be formed partially into the base dielectric layer. Preferably, the profile modifying dielectric layer has an etch removal rate between the first and second predetermined etch rates. If more than one of the profile modifying dielectric layers are to be used, it is preferred that their etch removal rates increase with increased distance from the wafer. Most preferably, the etch removal rates of all the dielectric layers continuously increase from the bottom to the top layer, so as to obtain a very smooth
Normally, it would have involved a relatively tedious and expensive procedure to attempt to deposit such a relatively large number of dielectric layers (i.e., the base dielectric layer, the bottom dielectric layer, the at least profile modifying dielectric layer, and the top dielectric layer) on the wafer. However, another important aspect of the present invention is that the formation of these multiplicity of dielectric layers can be effectuated in a relatively simple manner such that all of the dielectric layers are deposited in the same deposition process, with a minor change in the deposition condition.
More specifically, the present invention can take advantage of an observation that the etch removal rate (both dry and wet) of a dielectric layer deposited using the plasma-enhanced chemical-vapor-deposition (PECVD) process can be adjusted by adjusting one or two of the process parameters, such as the partial pressure of the reaction gas, th
Brown Charlotte A.
Liauh W. Wayne
Utech Benjamin L.
Winbond Electronics Corp.
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