Methods to gather and display pin congestion statistics...

Details Methods to gather and display pin congestion statistics... Methods to gather and display pin congestion statistics...

2007-09-25

2007-09-25

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

10866457

ABSTRACT:
The present invention is a method for collecting, analyzing, and displaying statistics regarding block pin placement prior to routing of an integrated circuit. The statistics are graphically displayed in a graphical user interface (GUI). The GUI graphically displays indications of where block pin congestion problems lie, which allows an integrated circuit designer to quickly pinpoint and correct pin placement in areas of pin congestion to alleviate congestion in these areas prior to routing.

REFERENCES:
patent: 5309372 (1994-05-01), Marui et al.
patent: 7065730 (2006-06-01), Alpert et al.
patent: 2001/0049814 (2001-12-01), Matsumoto et al.
patent: 2005/0138595 (2005-06-01), Khakzadi et al.

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