Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-09-09
2008-09-09
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
11279552
ABSTRACT:
A method is provided for determining a worst-case single cycle setup time between a first and second clock domain. First, an offset time of a second clock domain with respect to a first clock domain is normalized. A base period of the first clock domain and the second clock domain is then obtained. Next, a first greatest common denominator (GCD) shared by the first and second clock domains and the normalized second clock domain offset time is factored. Then, a reduced offset time and a reduced offset time size factor are substituted into an expression representing a relationship between the first and second clock domains. A second GCD shared by the first and second clock domains is factored from the expression and a modulus value of the reduced offset time and the second GCD is computed. Based on the modulus value, the worst-case single cycle setup time is computed.
REFERENCES:
patent: 7206958 (2007-04-01), Sutherland et al.
patent: 2004/0125487 (2004-07-01), Sternad et al.
patent: 2005/0119186 (2005-06-01), Larson
patent: 2007/0089076 (2007-04-01), Amatangelo
Altera Corporation
Chiang Jack
Martine & Penilla & Gencarella LLP
Memula Suresh
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