Methods to facilitate etch uniformity and selectivity

Details Methods to facilitate etch uniformity and selectivity Methods to facilitate etch uniformity and selectivity

2005-08-19

2008-03-11

Kebede, Brook (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S705000, C257SE21577

Reexamination Certificate

active

07341941

ABSTRACT:
A semiconductor device is fabricated with energy based process(es) that alter etch rates for dielectric layers within damascene processes. A first interconnect layer is formed over a semiconductor body. A first dielectric layer is formed over the first interconnect layer. An etch rate of the first dielectric layer is altered. A second dielectric layer is formed on the first dielectric layer. An etch rate of the second dielectric layer is then altered. A trench etch is performed to form a trench cavity within the second dielectric layer. A via etch is performed to form a via cavity within the first dielectric layer. The cavities are filled with conductive material and then planarized to remove excess fill material.

REFERENCES:
patent: 6831005 (2004-12-01), Ross
patent: 6893985 (2005-05-01), Goodner
patent: 6909195 (2005-06-01), Li et al.
patent: 6917108 (2005-07-01), Fitzsimmons et al.
patent: 2002/0084257 (2002-07-01), Bjorkman et al.
patent: 2002/0130416 (2002-09-01), Wang et al.
patent: 2002/0142577 (2002-10-01), Chung et al.

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