Methods to control the droop when powering dual mode...

Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...

Reexamination Certificate

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C232S009000

Reexamination Certificate

active

06919715

ABSTRACT:
A DC/DC converter100has a DAC40that receives a code associated with desired processor operating voltage and sets the reference voltage on its output41. The reference voltage (VDAC) is boosted by the buffer amplifier42to center the droop along the median load. A sensed current signal ICS22is proportional to the load current Io24and can be either inductor current, or switch current, or diode (or synchronous switch) current. In all cases it is scaled down by the factor of gain Gc. A droop control feedback circuit includes an error amplifier50. It has two inputs. In one embodiment the gain of the converter is by a signal inversely proportional to the processor clock frequency FCPU maxand transformed to the current IDROOP32that creates the voltage drop across the resistor R1. The other input is coupled to the buffer amplifier output. As a result, the output voltage of the converter50is inversely proportionally to the load current and is invariant to the processor clock frequency changes associated with the processor mode switchover. Other embodiments modify the gain of the error amplifier, or offset the gain and hold the amount of droop constant.

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