Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-03-21
2008-11-25
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07458050
ABSTRACT:
A method to cluster Boolean functions for clock gating according to various exemplary embodiments can include identifying at least two small gating groups within a clock tree representative of an electrical network and at least two gating functions of the at least two small gating groups, wherein the at least two gating functions are Boolean functions; performing hierarchical clustering on the at least two gating functions using a similarity measure that describes a distance between the at least two gating functions such that the clustering forms a merge function of a cluster generated and displayed in a form of a dendrogram; assigning to each gating domain a merit value according to a power consumption profile of the gating domain using a merit function; and partitioning the cluster into gating groups using the dendrogram to construct a directed acyclic graph to determine a partition which maximize the overall power saving.
REFERENCES:
patent: 6609228 (2003-08-01), Bergeron et al.
patent: 7225421 (2007-05-01), Migatz et al.
patent: 2007/0157130 (2007-07-01), Eisner et al.
Ding et al., “Cluster Mergining and Splitting in Hierarchical Clustering Algorithms”, Proceedings of 2002 IEEE International Conference on Data Mining, 2002, pp. 139-146.
Arbel Eli
Eisner Cynthia Rae
Fuhrmann Oded
Itskovich Alexander
Levitt David J.
Doster Greene, LLC
International Business Machines - Corporation
Kik Phallaka
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