Methods relating to trench-based support structures for...

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation

Reexamination Certificate

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C438S405000, C438S412000, C438S740000

Reexamination Certificate

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07923345

ABSTRACT:
A method of manufacturing a semiconductor device wherein a laminate structure comprising a sacrificial layer is sandwiched between two etch stop layers (8,11) and which separates a semiconductor membrane (9) from a bulk substrate (1) is used to provide an underetched structure. Access trenches (4) and support trenches (5) are formed in the layered structure through the thickness of the semiconductor layer (9) and through the upper etch stop layer (8). The support trenches extend deeper through the sacrificial layer (12) and the lower etch stop layer and are filled. The sacrificial layer is exposed and etched away selectively to the etch stop layers to form a cavity (30) and realise a semiconductor membrane which is attached to the bulk substrate via a vertical support structure comprising the filled support trenches.

REFERENCES:
patent: 6887391 (2005-05-01), Daneman et al.
patent: 6930027 (2005-08-01), Parthasarathy et al.
patent: 2004/0171233 (2004-09-01), Ohmi et al.
patent: 2005/0020085 (2005-01-01), Lee et al.
patent: 2006/0022269 (2006-02-01), Kato
patent: 3715232 (1988-11-01), None
patent: 0002235 (2000-01-01), None
patent: 2005093824 (2005-10-01), None
WIPO Publication No. WO 2006/109265 A1 to Sonsky.

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