Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-04-03
2001-10-30
Lefkowitz, Sumati (Department: 2181)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C707S793000
Reexamination Certificate
active
06311290
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of computer systems. In particular, this invention is drawn to management of nonvolatile memory.
BACKGROUND OF THE INVENTION
Initialization of a computer system is performed upon power-up of the computer system or hardware or software reset operations. The initialization process is referred to as “booting” the computer system.
In one boot scheme the processor is designed to read a pre-determined memory location when the processor is reset or powered up. The pre-determined memory location stores a boot vector which directs the processor to a memory address of the beginning of the bootstrap routines.
The boot vector typically defaults to an address in read-only memory (ROM). The ROM stores the computer system boot code such as the bootstrap loader and other initialization routines. The device storing the bootstrap loader and other minimal initialization procedures is referred to as the boot device.
Traditionally, ROM or EPROMs have served as nonvolatile memory for storage of computer system boot code. The boot code may include software such as Basic Input Output System (“BIOS”) routines which are specific to the computer system being booted. Thus system specific information is also stored in the ROM or EPROM.
One disadvantage of this approach, however, is the inability to reprogram the ROM or EPROM to accommodate changes in the computer system. The only way to make changes to the BIOS, for example, is to replace the ROM or EPROM. This may be difficult if the ROM or EPROM is soldered to a circuit board. In addition, the computer may have to be at least partially disassembled in order to gain access to the ROM or EPROM.
A programmable nonvolatile memory such as flash electrically erasable programmable read only memory (flash EEPROM) provides a medium that allows the BIOS to be adapted to changing hardware and software conditions. BIOS updates can be performed using an update program in order to modify the BIOS to accommodate, for example, new peripheral devices, additional memory, add-in cards or even to fix errors in the current version of the BIOS.
Flash memory can be reprogrammed only after being erased. Erasure of flash memory must be performed at a block level, thus in order to change a few bytes within a block, the entire block must first be erased. The bootstrap loader, BIOS, and system parameters can be located in separate blocks to facilitate independent modification.
The flash memory used to store boot code and BIOS is typically asymmetrically blocked due to the size differences between the bootstrap loader, BIOS, and system parameter data. Thus the bootstrap loader is stored in a block of one size and the BIOS is stored in one or more blocks of a different size. In addition, blocks storing system specific parameter data might be yet a third size.
One disadvantage of this approach is that asymmetrically blocked architectures are more difficult to expand or extend as the stored code or data changes in size. The block sizes are fixed when the nonvolatile memory is fabricated, thus the block sizes cannot subsequently be changed in order to allocate excess memory from one block to another block.
The asymmetrically blocked architecture typically results in wasted memory because there is no provision for management of the excess memory within individual blocks. BIOS update programs typically replace the contents of the block containing the old BIOS with the new BIOS. Thus any data sharing the same block as the BIOS will be lost when the BIOS is updated. This prevents other applications from being able to use excess memory within a block. Thus another disadvantage of the asymmetrically blocked architecture is the inability to use excess memory within a block.
When updating BIOS, the blocks that the BIOS is stored in must first be erased. If a power failure occurs after starting the erasure of the blocks and before the new version of the BIOS has been completely written, then the BIOS within the nonvolatile memory may be left in an unusable state. Furthermore, the computer system cannot recover by using the old BIOS because the old BIOS was deleted when the block was erased. Thus the upgrade process is inherently unreliable because of the inability to return to a former valid state if an error occurs while updating to the new state. Thus another disadvantage of the single and asymmetrical blocked architectures is the sensitivity of the update process to events such as a power failure.
SUMMARY OF THE INVENTION
In view of limitations of known systems and methods, methods of managing nonvolatile memory are provided. Methods of reliably allocating, de-allocating, re-allocating, and reclaiming space within a nonvolatile memory having a bifurcated storage architecture are described. Allocation, writing, reading, de-allocating, re-allocating, and reclamation are handled by a memory manager. The memory manager tracks the progress of each process during execution in order to detect whether a selected process was interrupted for purposes of recovery. The nonvolatile memory is recovered to a known state during initialization. Initialization includes the step of determining a recovery state from a recovery state lookup table. A selected recovery process is selected in accordance with the recovery state lookup table. A restart level for the selected process is determined from a corresponding restart state lookup table. The selected process is then restarted at the restart level.
In one embodiment, a method of managing a nonvolatile memory includes the step of identifying an interrupted process from at least one of an allocation, a reclamation, a configuration header reclaim, and a re-allocation process initiated on the nonvolatile memory. A recovery process is selected for the interrupted process. An entry point into the recovery process is determined. The selected recovery process is then restarted at the entry point.
REFERENCES:
patent: 4758944 (1988-07-01), Bartley et al.
patent: 4849878 (1989-07-01), Roy
patent: 5297148 (1994-03-01), Harari et al.
patent: 5333292 (1994-07-01), Takemoto et al.
patent: 5361343 (1994-11-01), Kosnocky et al.
patent: 5404485 (1995-04-01), Ban
patent: 5410707 (1995-04-01), Bell
patent: 5437020 (1995-07-01), Wells et al.
patent: 5479639 (1995-12-01), Ewertz et al.
patent: 5519831 (1996-05-01), Holzhammer
patent: 5519843 (1996-05-01), Moran et al.
patent: 5522076 (1996-05-01), Dewa et al.
patent: 5530673 (1996-06-01), Tobita et al.
patent: 5533190 (1996-07-01), Binford
patent: 5535357 (1996-07-01), Moran et al.
patent: 5535369 (1996-07-01), Wells et al.
patent: 5544356 (1996-08-01), Robinson et al.
patent: 5563828 (1996-10-01), Hasbun et al.
patent: 5579522 (1996-11-01), Christeson et al.
patent: 5581723 (1996-12-01), Hasbun et al.
patent: 5592669 (1997-01-01), Robinson et al.
patent: 5596738 (1997-01-01), Pope
patent: 5602987 (1997-02-01), Harari et al.
patent: 5603056 (1997-02-01), Totani
patent: 5625819 (1997-04-01), Hoffer, Jr.
patent: 5671388 (1997-09-01), Hasbun
patent: 5680570 (1997-10-01), Rantala et al.
patent: 5701492 (1997-12-01), Wadsworth et al.
patent: 5715423 (1998-02-01), Levy
patent: 5717886 (1998-02-01), Miyauchi
patent: 5734894 (1998-03-01), Hook et al.
patent: 5737742 (1998-04-01), Achiwa et al.
patent: 5829013 (1998-10-01), Hasbun
patent: 5933838 (1999-08-01), Lomet
patent: 5937434 (1999-08-01), Hasbun et al.
patent: 5974426 (1999-10-01), Lee et al.
patent: 6122733 (2000-09-01), Christeson et al.
patent: 6170066 (2001-01-01), See
“A TrueFFS and Flite Technical Overview of M-Systems'Flash File Systems”, M-Systems Technology Brief, Oct. 1996 (pp. 1-10).
Products Guide, M-Systems (reprinted Apr. 1997), (3 pgs.).
News & Events: Products, Partners and Corporate Press Release Index, M-Systems, (reprinted Apr. 11, 1997), (1 page).
“Intel and M-Systems Sign FLT Marketing Agreement”, News and Events Press Releases, M-Systems, Dec. 11, 1995 (2 pgs.)
“AMD Flash Card Products Supported by TrueFFS Software”, News and Events Press Releases, M-Systems, Mar. 24, 1997 (2 pgs.).
“M-Systems Ann
Edwards David A.
Gafken Andrew H.
Hasbun Robert N.
Spiegel Christopher J.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Lefkowitz Sumati
LandOfFree
Methods of reliably allocating, de-allocating,... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods of reliably allocating, de-allocating,..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of reliably allocating, de-allocating,... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2589273