Methods of reading and/or writing data to memory devices...

Details Methods of reading and/or writing data to memory devices... Methods of reading and/or writing data to memory devices...

2002-04-16

2004-01-06

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

C365S154000, C365S230050

Reexamination Certificate

active

06674670

ABSTRACT:

RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 2001-24685, filed May 7, 2001, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.
FIELD OF THE INVENTION
The present invention relates to semiconductor devices, and more particularly, to semiconductor memory devices and related methods.
BACKGROUND OF THE INVENTION
FIG. 1
is a diagram illustrating a conventional semiconductor memory cell connected to a write word line and a read word line. Referring to
FIG. 1
, the conventional semiconductor memory cell connected to a write word line AWWL
1
and a read word line ARWL
1
includes a latch circuit A
120
, a write circuit A
140
, a first read circuit A
110
, and a second read circuit A
130
.
The latch circuit A
120
includes two PMOS transistors AP
1
and AP
2
and two NMOS transistors AN
1
and AN
2
, thereby latching a predetermined external voltage applied to a first node AND
1
. The write circuit A
140
transmits a predetermined voltage loaded in a write bit line AWBL
1
to the first node AND
1
of the latch circuit A
120
in response to the write word line AWWL
1
.
The first read circuit A
110
inverts the voltage level at the first node AND
1
in response to the read word line ARWL
1
and transmits the voltage to a read bit line ARBL
1
. The second read circuit A
130
inverts the voltage level at a second node AND
2
in response to the read word line ARWL
1
and transmits the voltage to a complementary read bit line ARBLB
1
.
The conventional semiconductor memory device of
FIG. 1
includes a plurality of semiconductor memory cells arranged in row and column directions.
FIG. 2
is a diagram illustrating a conventional semiconductor memory cell connected to a write word line and two read word lines. Referring to
FIG. 2
, the conventional semiconductor memory cell connected to a write word line AWWL
1
and two read word lines ARWL
1
and ARWL
2
includes a latch circuit A
220
, a write circuit A
240
, a first read circuit A
210
, and a second read circuit A
230
.
The latch circuit A
220
includes two PMOS transistors AP
1
and AP
2
and two NMOS transistors AN
1
and AN
2
, thereby latching a predetermined external voltage applied to a first node AND
1
. The write circuit A
240
transmits a predetermined voltage loaded in a write bit line AWBL
1
to the first node AND
1
of the latch circuit A
220
in response to the write word line AWWL
1
.
The first read circuit A
210
inverts the voltage level of the first node AND
1
in response to a first read word line ARWL
1
and/or a second read word line ARWL
2
and transmits the voltage to a first read bit line ARBL
1
and/or a second read bit line ARBL
2
. The second read circuit A
230
inverts the voltage level of a second node AND
2
in response to a first read word line ARWL
1
and/or a second read word line ARWL
2
and transmits the voltage to a first complementary read bit line ARBLB
1
and/or a second complementary read bit line ARBLB
2
. The conventional semiconductor memory device of
FIG. 2
includes a plurality of semiconductor memory cells arranged in row and column directions.
Referring to
FIG. 1
, the operation of the conventional semiconductor memory cell will be described. In a case where a logic high state “H” is recorded at the first node AND
1
of the latch circuit A
120
, the write word line AWWL
1
is controlled to activate the write circuit A
140
, the first node AND
1
is charged with an electrical charge representing the state “H” of the write bit line AWBL
1
through the write circuit A
140
.
In a case where a logic low state “L” is recorded at the first node AND
1
of the latch circuit A
120
, the write word line AWWL
1
is controlled to activate the write circuit A
140
, and an electrical charge stored in the first node AND
1
is discharged into the write bit line AWBL
1
through the activated write circuit A
140
.
The voltage level at the first node AND
1
and/or the second node AND
2
of the latch circuit A
140
is output to an external device through the read bit line ARBL
1
and the complementary read bit line ARBLB
1
through the first read circuit A
110
and/or the second read circuit A
130
.
Responsive to a signal of the read word line ARWL
1
, the first read circuit A
110
inverts the voltage level at the first node AND
1
and transmits the voltage level to the read bit line ARBL
1
. Since the read bit line ARBL
1
is pre-charged to the state “H”, the voltage level of the read bit line ARBL
1
is not changed if the voltage level at the first node AND
1
is in the state “H”. However, if the voltage level at the first node AND
1
is in the state “L”, an electrical charge of the read bit line ARBL
1
is discharged into a supply voltage Vss through transistors AN
5
and AN
3
of the first read circuit A
110
, and thus, the first read bit line ARBL
1
represents the state “L”.
The second read circuit A
130
responding to a signal of the read word line ARWL
1
inverts the voltage level at the second node AND
2
and transmits the voltage to a first complementary read bit line ARBLB
1
. A method for inverting the voltage level of the second node AND
2
and transmitting the voltage to the first complementary read bit line ARBLB
1
is the same as a method for reading the voltage level at the first node AND
1
by using the first read circuit A
110
.
The conventional semiconductor memory cells shown in
FIGS. 1 and 2
, however, may have disadvantages. If the first write word line AWWL
1
is selected from a plurality of write word lines AWWL
1
through AWWLN (not shown) and is in a state “H”, for example, a plurality of latch circuits A
140
and A
240
, which are controlled by the first write word line AWWL
1
, are all activated. The voltage level of the write bit line AWBL
1
should be applied only to the latch circuits A
120
and A
220
which are connected to one write circuit from the plurality of write circuits A
140
and A
240
. However, charge re-distribution may occur even in the latch circuits A
120
and A
220
which are connected to the other write circuits. Thus, errors such as data being recorded in an unselected semiconductor memory cell may occur.
In a case where the read word lines ARWL
1
and/or ARWL
2
are in the state “H” during a read operation, one of the read bit line pairs ARBL
1
and/or ARBL
2
which has been already charged to the state “H” may be discharged regardless of the data stored in the latch circuits A
120
and A
220
, resulting in unnecessary power consumption. This is a reason the first node AND
1
and the second node AND
2
have opposite voltage levels.
In addition, if charges of the second read bit line ARBL
2
and the second complementary read bit line ARBLB
2
are increased (see FIG.
2
), assuming that the first read word line ARWL
1
and the second read word line ARWL
2
are simultaneously in the state “H”, an effective capacitance of a third node AND
3
, which is connected to both read bit lines ARBL
1
and ARBL
2
, may increase, thereby increasing read time.
SUMMARY OF THE INVENTION
According to embodiments of the present invention, methods can be provided for reading data from a memory device comprising a plurality of memory cells and a plurality of virtual ground lines wherein each memory cell comprises a latch circuit coupled to a read circuit and wherein each virtual ground line is coupled with read circuits of a respective group of memory cells. Methods for reading according to embodiments of the present invention can include selecting a memory cell from which data is to be read, applying a first reference voltage to a virtual ground line coupled to the selected memory cell from which data is to be read, and applying a second reference voltage to a virtual ground line not coupled to the selected memory cell. A read word line coupled to the read circuit of the selected memory cell from which data is to be read can be activated. Responsive to activating the read word line coupled to the read circuit of the selected memory cell from which data is to be read, data can

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