Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2008-04-22
2008-04-22
Tran, Anh Q (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S026000, C326S027000, C326S041000
Reexamination Certificate
active
11449198
ABSTRACT:
Methods of compensating for process variations in an integrated circuit. Multiplexer circuits can be programmed to balance the rising and falling delays through the circuits in the presence of process variations. These multiplexer circuits can be used, for example, as programmable interconnect multiplexers in the interconnect structures of PLDs. During wafer sort or final test, a process corner can be determined for each die. One or more E-fuses can be set to predetermined level(s) to program the process corner information into the die, or the values can be stored in some other type of non-volatile memory. The stored values are utilized by the programmable multiplexer circuits to optionally adjust the rising and/or falling delays through the multiplexer circuits to achieve a balance between the rising and falling delays.
REFERENCES:
patent: 5589783 (1996-12-01), McClure
patent: 6177819 (2001-01-01), Nguyen
patent: 6236231 (2001-05-01), Nguyen et al.
patent: 6476638 (2002-11-01), Zhou et al.
patent: 7020764 (2006-03-01), Kubota et al.
patent: 7064582 (2006-06-01), Gallo et al.
patent: 7215150 (2007-05-01), Torres et al.
patent: 7227390 (2007-06-01), Bapat et al.
patent: 7248083 (2007-07-01), Chung
patent: 2004/0113654 (2004-06-01), Lundberg
patent: 2006/0119384 (2006-06-01), Camarota et al.
patent: 2007/0040577 (2007-02-01), Lewis et al.
U.S. Appl. No. 11/449,172, filed Jun. 8, 2006, Schultz.
U.S. Appl. No. 11/449,202, filed Jun. 8, 2006, Rahman.
U.S. Appl. No. 11/449,203, filed Jun. 8, 2006, Rahman.
U.S. Appl. No. 11/449,240, filed Jun. 8, 2006, Schultz.
Arifur Rahman et al.; “Heterogeneous Routing Architecture for Low-Power FPGA Fabric”; IEEE 2005 Custom Integrated Circuits Conference; Copyright 2005 IEEE; pp. 183-186.
Cartier Lois D.
Tran Anh Q
LandOfFree
Methods of providing performance compensation for process... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods of providing performance compensation for process..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of providing performance compensation for process... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3915132