Methods of providing an interlevel dielectric layer...

Details Methods of providing an interlevel dielectric layer... Methods of providing an interlevel dielectric layer...

1999-08-03

2002-02-26

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S618000, C438S622000, C438S623000, C438S631000, C438S645000, C438S647000, C438S648000

Reexamination Certificate

active

06350679

ABSTRACT:

TECHNICAL FIELD
This invention relates to methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry.
BACKGROUND OF THE INVENTION
In methods of forming integrated circuits, it is frequently desired to electrically isolate components of the integrated circuits from one another with an insulative material. For example, conductive layers can be electrically isolated from one another by separating them with an insulating material. Insulating material received between two different elevation conductive or component layers is typically referred to as an interlevel dielectric material. Also, devices which extend into a semiconductive substrate can be electrically isolated from one another by insulative materials formed within the substrate between the components, such as for example, trench isolation regions.
One typical insulative material for isolating components of integrated circuits is silicon dioxide, which has a dielectric constant of about 4. Yet in many applications, it is desired to utilize insulative materials having dielectric constants lower than that of silicon dioxide to reduce parasitic capacitance from occurring between conductive components separated by the insulative material. Parasitic capacitance reduction continues to have increasing importance in the semiconductor fabrication industry as device dimensions and component spacing continues to shrink. Closer spacing adversely effects parasitic capacitance.
One way of reducing the dielectric constant of certain inherently insulative materials is to provide some degree of carbon content therein. One example technique for doing so has recently been developed by Trikon Technology of Bristol, UK which they refer to as Flowfill™ Technology. Where more carbon incorporation is desired, methylsilane in a gaseous form and H
2
O
2
in a liquid form are separately introduced into a chamber, such as a parallel plate reaction chamber. A reaction between the methylsilane and H
2
O
2
can be moderated by introduction of nitrogen into the reaction chamber. A wafer is provided within the chamber and ideally maintained at a suitable low temperature, such as 0° C., at a exemplary pressure of 1 Torr to achieve formation of a methylsilanol structure. Such structure/material condenses on the wafer surface. Although the reaction occurs in the gas phase, the deposited material is in the form of a viscus liquid which flows to fill small gaps on the wafer surface. In applications where deposition thickness increases, surface tension drives the deposited layer flat, thus forming a planarized layer over the substrate.
The liquid methylsilanol is converted to a silicon dioxide structure by a two-step process occurring in two separate chambers from that in which the silanol-type structure was deposited. First, planarization of the liquid film is promoted by increasing the temperature to above 100° C., while maintaining the pressure at about 1 Torr, to result in solidification and formation of a polymer layer. Thereafter, the temperature is raised to approximately 450° C., while maintaining a pressure of about 1 Torr, to form (CH
3
)
y
SiO
(2−y)
. y/2 is the percentage of CH
3
incorporated. The (CH
3
)
y
SiO
(2−y)
has a dielectric constant of less than or equal to about 3, and is accordingly less likely to be involved in parasitic capacitance than silicon dioxide and/or phosphorous doped silicon dioxide.
Other example low k dielectric layer materials include fluorine doped silicon dioxide, high carbon and hydrogen containing materials, and other organic films having less than 20% silicon.
A prior art problem associated with low k dielectric material usage is that many of these materials cannot withstand high temperature processing. Specifically, many melt or gassify at comparatively low temperatures at which the substrate is subjected after deposition of the low k materials. This can essentially destroy the circuitry being fabricated. It is further very difficult to quickly strip photoresist when processing over such low k dielectric layers, as the typical photoresist stripping processes undesirably cause some isotropic etching of the low k dielectric layers.
SUMMARY
The invention comprises methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry. In one implementation, a method of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry includes forming a conductive metal interconnect layer over a substrate. An insulating dielectric mass is provided about the conductive metal interconnect layer. The insulating dielectric mass s has a first dielectric constant. At least a majority of the insulating dielectric mass is etched away from the substrate. After the etching, an interlevel dielectric layer is deposited to replace at least some of the etched insulating dielectric material. The interlevel dielectric layer has a second dielectric constant which is less than the first dielectric constant.


REFERENCES:
patent: 3919060 (1975-11-01), Pogge et al.
patent: 3954523 (1976-05-01), Magdo et al.
patent: 3979230 (1976-09-01), Anthony et al.
patent: 3998662 (1976-12-01), Anthony et al.
patent: 4063901 (1977-12-01), Shiba
patent: 4180416 (1979-12-01), Brock
patent: 4561173 (1985-12-01), Te Velde
patent: 5023200 (1991-06-01), Blewer et al.
patent: 5103288 (1992-04-01), Sakamoto et al.
patent: 5141896 (1992-08-01), Katoh
patent: 5149615 (1992-09-01), Chakravorty et al.
patent: 5171713 (1992-12-01), Matthews
patent: 5192834 (1993-03-01), Yamanishi et al.
patent: 5266519 (1993-11-01), Iwamoto
patent: 5286668 (1994-02-01), Chou
patent: 5461003 (1995-10-01), Havemann et al.
patent: 5464786 (1995-11-01), Figura et al.
patent: 5470801 (1995-11-01), Kapoor et al.
patent: 5488015 (1996-01-01), Havermann et al.
patent: 5496773 (1996-03-01), Rhodes et al.
patent: 5525857 (1996-06-01), Gnade et al.
patent: 5527737 (1996-06-01), Jeng
patent: 5554567 (1996-09-01), Wang
patent: 5559666 (1996-09-01), Figura et al.
patent: 5583078 (1996-12-01), Osenbach
patent: 5599745 (1997-02-01), Reinberg
patent: 5629238 (1997-05-01), Choi et al.
patent: 5654224 (1997-08-01), Figura et al.
patent: 5670828 (1997-09-01), Cheung et al.
patent: 5691565 (1997-11-01), Manning
patent: 5691573 (1997-11-01), Avanzino et al.
patent: 5736425 (1998-04-01), Smith et al.
patent: 5744399 (1998-04-01), Rostoker et al.
patent: 5773363 (1998-06-01), Derderian et al.
patent: 5804508 (1998-09-01), Gnade et al.
patent: 5807607 (1998-09-01), Smith et al.
patent: 5808854 (1998-09-01), Figura et al.
patent: 5861345 (1999-01-01), Chou et al.
patent: 5882978 (1999-03-01), Srinivasan et al.
patent: 5883014 (1999-03-01), Chen et al.
patent: 5950102 (1999-09-01), Lee
patent: 5970360 (1999-10-01), Cheng et al.
patent: 6001747 (1999-12-01), Annapragada
patent: 6028015 (2000-02-01), Wang et al.
patent: 6156374 (2000-12-01), Forbes et al.
patent: 6251470 (2001-06-01), Forbes et al.
patent: 0 542 262 (1993-05-01), None
patent: 0 923 125 (1999-06-01), None
patent: 0923125 (1999-06-01), None
Gayet et al., Translation of EP 0923125 A1, “Process For Making Metal Interconnections In Integrated Circuits”, Jun. 1999.*
U.S. application No. 08/947,360, Werner et al., filed Oct. 9, 1997.
Yoon et al, Monolithic Integration of 3-D Electroplated Microstructures with Unlimited Number of Levels . . . IEEE International Micro-Electro Mechanical Systems Conference (1999) pp. 624-629.
Wolf et al., “Silicon Processing for the VLSI Era”, 1 Process Technology 429-437 (1986).
Watanabe et al., A Novel Stacked Capacitor With Porous-Si Electrodes for High Density DRAMS, Microelectronics Research Laboratories, NEC Corporation, Japan, #3A-1, pp. 17-18 (pre-1998).
“Monolithic Integration of 3-D Electroplated Microstuctures with Unlimited Number of Levels Using Planariaztion with a Sacrificial Metallic Mold”, Yoon et al.; IEEE International Micro-Electro Mechani

Affiliated with

Also associated with

Rating

Methods of providing an interlevel dielectric layer... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods of providing an interlevel dielectric layer..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of providing an interlevel dielectric layer... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2944403