Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-07-13
2009-02-17
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
07493585
ABSTRACT:
A method for technology mapping user logical RAM on a programmable logic device is provided. The method preferably includes clustering non-RAM functional block types in the programmable logic device. Following synthesis of a user design, the method then includes determining the number of physical RAM locations available on the selected device. Also, the method includes determining the number of physical RAM locations available in the PLD and the number of Look-Up-Table (LUT) RAM locations available in the PLD. Finally, the method includes determining a combination of physical RAM locations and LUT RAM locations for implementation of the user logical RAM. The combination preferably represents a beneficial combination of physical RAM and LUT RAM with respect to a predetermined metric.
REFERENCES:
patent: 6732348 (2004-05-01), Tahoori et al.
patent: 6817006 (2004-11-01), Wells et al.
patent: 6871328 (2005-03-01), Fung et al.
patent: 7143376 (2006-11-01), Eccles
patent: 7171633 (2007-01-01), Hwang et al.
Ahmed Elias
Padalia Ketan
Altera Corporation
Bowers Brandon W
Chiang Jack
Jackson Robert R.
Ropes & Gray LLP
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