Methods of operating memory devices including negative...

Details Methods of operating memory devices including negative... Methods of operating memory devices including negative...

2008-01-29

2009-12-15

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185170, C365S185180, C365S185210, C365S185220

Reexamination Certificate

active

07633803

ABSTRACT:
A memory device may include a plurality of memory cell transistors serially coupled in a string between a string selection transistor and a ground selection transistor. Moreover, the string selection transistor may be coupled between the string and a bitline, and the ground selection transistor may be coupled between the string and a common source line. During programming, one of the plurality of memory cell transistors in the string may be selected for a program operation so that other memory cell transistors in the string are unselected, and a plurality of negative voltage pulses may be applied to a channel region of the selected memory cell transistor. While applying the plurality of negative voltage pulses to the channel region, a positive pass voltage may be applied to control gate electrodes of the unselected memory cell transistors, and a positive program voltage may be applied to a control gate electrode of the selected memory cell. Related methods and devices are discussed.

REFERENCES:
patent: 5473563 (1995-12-01), Suh et al.
patent: 5642309 (1997-06-01), Kim et al.
patent: 5696717 (1997-12-01), Koh
patent: 5781483 (1998-07-01), Shore
patent: 5812457 (1998-09-01), Arase
patent: 6005804 (1999-12-01), Hollmer et al.
patent: 6522580 (2003-02-01), Chen et al.
patent: 6671204 (2003-12-01), Im
patent: 2002/0060926 (2002-05-01), Choi et al.
patent: 2002/0158282 (2002-10-01), Li et al.
patent: 2006/0050561 (2006-03-01), Guterman et al.
patent: 2006/0140012 (2006-06-01), Wan et al.
patent: 2006/0171209 (2006-08-01), Sim et al.
patent: 2006/0227618 (2006-10-01), Lee
patent: 2007/0002629 (2007-01-01), Lee et al.
patent: 2007/0081388 (2007-04-01), Joo
patent: 2008/0151633 (2008-06-01), Park et al.
patent: 2009/0097321 (2009-04-01), Kim et al.
patent: 7-57486 (1995-03-01), None
patent: 1020050073297 (2005-07-01), None
patent: 1020060040381 (2006-05-01), None
patent: 10-2007-0000525 (2007-01-01), None
patent: 1020070002411 (2007-01-01), None
patent: 10-2007-0034305 (2007-03-01), None
patent: WO 2004/061861 (2004-07-01), None
patent: WO 2004/061861 (2004-07-01), None
United Kingdom Search Report (5 pages) corresponding to United Kingdom Patent Application No. GB0808456.8; Dated: Aug. 28, 2008.
128M × 8 Bit NAND Flash Memory, K9K1G08R0B, K9K1G08B0B, K9K1G08U0B, Samsung Electronics Co., Ltd., 41 pages, Mar. 17, 2003.

Affiliated with

Also associated with

Rating

Methods of operating memory devices including negative... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods of operating memory devices including negative..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of operating memory devices including negative... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4103912