Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Self-aligned
Reexamination Certificate
1998-07-13
2003-08-26
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Self-aligned
C438S327000, C438S329000, C438S375000
Reexamination Certificate
active
06610578
ABSTRACT:
The present invention relates to manufacturing IC components suited for signals within the radio frequency range and manufactured using bipolar technology based on silicon (Si), in particular for simultaneously manufacturing vertical NPN-transistors, capacitors and lateral PNP-transistors on a silicon substrate and for producing deep substrate contacts.
BACKGROUND
Nowadays it is possible to produce fast bipolar circuits having a high packing density by using bipolar transistors (Bip-transistors) which are manufactured having two layers of polysilicon and thus are transistors of the so called double poly-Si-type, using self-aligning or self-aligning technology combined with electrical isolation provided by trenches surrounding the transistor, so called trench isolation. A schematic cross-sectional view of such a previously known trench isolated bipolar transistor of “double poly-Si-type”, which is manufactured using self-aligning technology, is shown in FIG.
1
.
In the known manufacturing process for bipolar transistors of double poly-Si-type one lets the first deposited polysilicon layer form a base connection. If the transistor is NPN-type, this poly-Si-layer is doped strongly to type P. The last deposited polysilicon layer, which is doped strongly to type N and forms an emitter electrode, is physically separated from the first deposited polysilicon layer forming the base connection by an underlying electrically isolating layer and isolating side-strings, also called “spacers”. The advantage of the self-aligning method when manufacturing bipolar transistors is that both the base resistance and the capacitance between base and collector are reduced. Furthermore, the introduction of isolation provided by trenches drastically reduces the capacitance between collector and substrate. Thereby, circuit performances are considerably improved.
Hereinafter, a frequently used, known way of manufacturing a trench-isolated bipolar transistor of NPN-type will be described in detail with reference to
FIGS. 2
to
6
, which schematically show the production method. As a base material a monocrystalline silicon substrate
101
of type P is used having its surface located in a (100)-plane of the silicon crystal structure, see FIG.
2
. The bottom diffusion
102
which is a so called “buried layer” and which can be constituted of for example an ion implanted layer of arsenic or antimony, is lithographically defined, after which an epitaxial silicon layer
103
having a thickness of about a couple of &mgr;m is applied to the plate
101
. Thereafter N- and P-areas are defined on the plate
101
using lithography combined with ion implantation. The N-areas
104
, which are produced by ion implantation using e.g. phosphorous, are placed directly above the bottom diffusion
102
of type N+. Other areas
105
, which are located between the N-areas
104
, are P-doped and are manufactured by e.g. ion implantation of boron, see FIG.
2
.
Then the active areas are defined by means of conventional LOCOS-methods (“LOCal Oxidation of Silicon”), see J. A. Appel et al., “Local oxidation of silicon and its application in semiconductor technology”, Philips Research Report, Vol. 25, 1970, pp. 118-132. Then first an isolating mask
106
of a suitable material is applied, see
FIG. 3
, which is then lithographically patterned. After that silicon
107
is thermally grown in the apertures in the mask
106
, so that a base area
108
and a collector area
109
for the transistor to be produced remain and are formed within the areas, where the mask covers the surface. After thus having defined the active areas, separated by an oxide layer area
109
′, and having removed the mask layer
106
, isolating trenches
110
are lithographically defined, the windows in the trench etching mask, not shown, being placed at the boundary line between the N-type epitaxial areas
104
and the P-type epitaxial areas, whereafter the thermally grown silicon oxide material
107
and the substrate material
101
are etched away in said windows using isotropic dry etching, until the trenches
110
have acquired a desired depth, about 5 to 10 &mgr;m, and extend down into the non-affected P-substrate
101
.
The walls of the trenches
110
are then thermally oxidized, so that a thin, electrically isolating layer, not shown, is obtained, after which the trenches are filled with an isolating or semi-isolating material
111
, for example silicon oxide or polycrystalline silicon, also called poly-Si or polysilicon. The filling material is then etched away by dry etching until a flat surface is obtained. Then the surface of the plate is oxidized and in particular the silicon material in the openings of the trenches
110
is oxidized in the case where the trenches have been filled polysilicon, in order to obtain an isolating layer, not shown, at the surface of the openings. If the trenches
110
are already, from the start, filled with only oxide, no such extra oxidizing step is required. The result is shown in FIG.
3
. It can be observed that the extension of the base area
108
in
FIG. 3
is defined using LOCOS-methods according to the discussion above. The drawback of this method will be discussed later, among other things in conjunction with a description of a modified process for manufacturing a transistor.
After forming the trenches
110
a collector plug
112
is lithographically defined, see
FIG. 4
, i.e. a low resistance connection between the surface of the component plate and the bottom diffusion
102
, within the collector area
109
. After that a dopant is applied, usually phosphorous, by ion implanting in the lithographically defined openings.
The description of the continued manufacturing process will be made for the above mentioned NPN-transistor of double poly-Si-type having a self-aligned base-emitter junction, since this component type is usually combined with electrical isolation obtained by trenches.
After the definition of active areas
108
,
109
, see
FIG. 2
, and forming a collector plug
112
as described above, a thin layer
113
of polysilicon is deposited having a thickness of some hundreds of nm, see FIG.
4
. The polysilicon layer
113
is then doped to become type P+ by ion implanting boron, after which a thin silicon oxide layer
114
is deposited on top of the polysilicon layer by means of CVD (“Chemical Vapour Deposition”). This polysilicon layer of type P+ doped with boron will after the finished manufacture form a so called extrinsic base
113
′ or base connection or base terminal by the diffusion of dopant into the surface layer of the N-epitaxial area
104
directly under the polysilicon layer
113
. The oxide layer
114
produced by CVD and the polysilicon layer
113
located thereunder are lithographically patterned in order to define an emitter opening
115
located within the base area
108
. Thereafter those portions of these two layers are removed, which are not covered by the lithographic mask, not shown, by a dry etching method such as plasma etching. After patterning the emitter opening
115
a thin thermal oxide
116
is grown for protecting the surface in the emitter opening, whereafter a so called intrinsic base, indicated by the crosses
117
, is produced by ion implanting boron. The intrinsic base
117
is thus located precisely in and beneath the emitter opening
115
.
In order to separate the emitter to be produced from the extrinsic base “spacers” or side strings
118
are formed along the sides of the emitter opening
115
, see FIG.
5
. This is made by first depositing an oxide layer by CVD conformally over the plate, after which an anisotropic dry etching procedure is used to etch away this oxide layer on the flat surface portions of the plate. Thereby a side string or spacer
118
of CVD oxide is formed along those steps which are formed when making the patterning for producing the emitter opening
115
. After forming such spacers
118
a thin polysilicon layer
119
is deposited having a thickness of some hundreds of nm on the surface of the plate. This la
Norström Hans
Nygren Stefan
Tylstedt Ola
Burns Doane Swecker & Mathis L.L.P.
Lattin Christopher
Niebling John F.
Telefonaktiebolaget LM Ericsson (publ)
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