Methods of manufacturing and testing integrated circuit field ef

Details Methods of manufacturing and testing integrated circuit field ef Methods of manufacturing and testing integrated circuit field ef

1998-04-27

2000-11-21

Bowers, Charles

Semiconductor device manufacturing: process

Including control responsive to sensed condition

Electrical characteristic sensed

H01L 2100

Patent

active

061501859

ABSTRACT:
Scanning Electron Microscope (SEM) analysis is used to detect undesired conductive material on the gate sidewall spacers. The undesired conductive material is then etched from the sidewall spacers if the undesired material is detected by the SEM analysis. More specifically, integrated circuit field effect transistors may be manufactured by forming on an integrated circuit substrate, a plurality of field effect transistors, each comprising spaced apart source and drain regions, a gate therebetween including a sidewall, a sidewall spacer on the sidewall and contacts comprising conductive material on the source and drain regions. At least one of the field effect transistors may include undesired conductive material on the sidewall spacer thereof. The integrated circuit field effect transistors are tested by performing SEM analysis on the integrated circuit substrate to detect the undesired conductive material on the sidewall spacer. The undesired conductive material is then etched from the sidewall spacer if the undesired material is detected by the SEM analysis.

REFERENCES:
patent: 5665203 (1997-09-01), Lee et al.

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