Methods of making hard macro cell using timing interval

Details Methods of making hard macro cell using timing interval Methods of making hard macro cell using timing interval

1999-10-07

2002-08-13

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06434727

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of making a hard macro cell for use in a semiconductor chip design, a design method of a semiconductor chip with using the hard macro cell, and a storage medium having data expressing a configuration of the hard macro cell.
2. Description of the Related Art
A hard macro cell is a circuit module which has a desired function, an optimum configuration, and a fixed mask pattern. A hard macro cell is registered in a cell library stored in a storage device and used as a component, as it is, in a design stage of a semiconductor chip. A hard macro cell can be handled by a user in a similar manner to those in a cell library in which other cells are registered. Adopting a hard macro cell in design of a semiconductor chip, logic design, logic verification, circuit synthesizing and layout design can be simplified, whereby it is expected that design man-days can be greatly reduced.
FIG. 7
is a schematic circuit diagram showing a concrete example of a prior art hard macro cell
10
.
The data input end DI of the hard macro cell
10
is connected to the data input end D of a D flip-flop
11
and the clock input end CK of the hard macro cell
10
is connected to the clock input end CK of the D flip-flop
11
by way of a buffer gate
12
. The data output end DO of the hard macro cell
10
is connected to the data output end Q of the D flip-flop
13
and the clock input end CK of the D flip-flop
13
is connected to the clock input end CK of the hard macro cell
10
. A circuit
14
which works so as to perform the desired function of the hard macro cell
10
is connected between the D flip-flops
11
and
13
. The circuit
14
runs in or out of synchronization with the clock CLK.
FIG. 8
is a diagram showing part of a circuit designed on a semiconductor chip CPO using the hard macro cell
10
.
Timing adjustment has already been performed within the hard macro cell
10
. However, what circuit or circuits are connected to the hard macro cell
10
is indefinite in a stage of making the hard macro cell
10
. Therefore, timing adjustment is necessary between the hard macro cell
10
and other circuits when the hard macro cell
10
is adopted in a design of a semiconductor chirp.
In
FIG. 8
, in order to adjust timing, a delay cell
21
is connected between the data output end Q of a D flip-flop
20
and the data input end DI of the hard macro cell
10
and a delay cell
23
is connected between the data output end DO of the hard macro cell
10
and the data input end D of a D flip-flop
22
. A clock CLK is commonly provided to the clock input ends CK of the hard macro cell
10
and the D flip-flops
20
and
22
.
Since a prior art hard macro cell is not designed with clear specifications covering external AC characteristics, a possibility has been high that a timing error occurs in the vicinity of the input/output ends of the hard macro cell
10
in a timing margin check after a chip layout design of a semiconductor chip using such a hard macro cell
10
. For this reason, in order to eliminate the timing error, a delay cell is inserted after layout design is finished or layout is performed again, thereby causing design time to be long.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of making a hard macro cell, a method of designing a semiconductor chip with using the same and a storage medium having data of the same, all of which make it possible to simplify design of a semiconductor chip with using the hard macro cell.
In the present invention, there is provided a method of making a hard macro cell, the hard macro cell having a data input end, a clock input end, and an internal synchronous flip-flop, the data input end of the hard macro cell being connected to a data input end of the internal synchronous flip-flop directly or by way of a combinational circuit, the method comprising the steps of: specifying an interval between an edge time point of a signal at the data input end of the hard macro cell and an active edge time point of a signal at the clock input end of the hard macro cell; and connecting a delay cell between the data input end of the hard macro cell and the data input end of the internal synchronous flip-flop so that no timing error occurs in the internal synchronous flip-flop if the specified interval is satisfied.
With the present invention, when a user performs semiconductor design using a hard macro cell or hard macro cells which are made by the method, a delay cell is not necessary to be inserted between the data input end of the hard macro cell and the external circuit, or it is possible to insert a delay cell having a predetermined delay time may, whereby an advantage of use of a hard macro cell to simplify a design is further increased to achieve a shorter design time.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.


REFERENCES:
patent: 6216256 (2001-04-01), Inoue

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