Methods of isolating array features during pitch doubling...

Details Methods of isolating array features during pitch doubling... Methods of isolating array features during pitch doubling...

2010-04-13

2010-12-21

Everhart, Caridad M (Department: 2895)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S945000, C257S775000, C257SE21036, C257SE21039

Reexamination Certificate

active

07855148

ABSTRACT:
Methods of isolating spaces formed between features in an array during a pitch reduction process and semiconductor device structures having the same. In one embodiment, ends of the features are wider than middle regions of the features. During the pitch reduction process, spacer sidewalls formed between adjacent ends of the features come into substantial contact with one another, isolating the spaces between the features. In another embodiment, the features have a single width and an additional feature is located near ends of the features. Spacer sidewalls formed between adjacent features and the additional feature come into substantial contact with one another, isolating the spaces between the features.

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