Methods of initializing routing structures in integrated...

Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral configuration

Reexamination Certificate

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C710S104000, C710S105000, C326S038000

Reexamination Certificate

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07743175

ABSTRACT:
Methods of initializing an integrated circuit (IC) in which the routing structures have data lines and handshake circuitry are provided. A node of each of the data lines is driven to a predetermined value, and the handshake circuit is disabled by disabling an acknowledge path within the handshake circuitry, e.g., by forcing all acknowledge signals in the acknowledge path to signal an acknowledgement of received data. The disablement causes the predetermined value to propagate throughout the data lines. The handshake circuitry is then enabled by enabling the acknowledge path, which releases the data lines to assume values determined by operation of the IC. When the IC is a programmable IC, configuration values may be programmed into the IC after disabling the acknowledge path and before enabling the handshake circuitry. When the handshake circuitry is enabled, the data lines assume initial values determined by the programmed configuration values.

REFERENCES:
patent: 4533994 (1985-08-01), Harrill et al.
patent: 4631698 (1986-12-01), Walsh et al.
patent: 5208491 (1993-05-01), Ebeling et al.
patent: 5261083 (1993-11-01), Witkowski et al.
patent: 5367209 (1994-11-01), Hauck et al.
patent: 5675524 (1997-10-01), Bernard
patent: 5787007 (1998-07-01), Bauer
patent: 6486709 (2002-11-01), Sutherland et al.
patent: 6522170 (2003-02-01), Durham et al.
patent: 6590424 (2003-07-01), Singh et al.
patent: 6958627 (2005-10-01), Singh et al.
patent: 7100168 (2006-08-01), Wenzl
patent: 7157934 (2007-01-01), Teifel et al.
patent: 7504851 (2009-03-01), Manohar et al.
patent: 7505304 (2009-03-01), Manohar et al.
patent: 2006/0087341 (2006-04-01), Plants et al.
patent: 2007/0253240 (2007-11-01), Manohar et al.
patent: 2007/0256038 (2007-11-01), Manohar
patent: 2007/0262786 (2007-11-01), Manohar et al.
patent: 2008/0168407 (2008-07-01), Manohar
U.S. Appl. No. 12/417,007, filed Apr. 2, 2009, Young et al.
U.S. Appl. No. 12/417,010, filed Apr. 2, 2009, Young.
U.S. Appl. No. 12/417,012, filed Apr. 2, 2009, Young.
U.S. Appl. No. 12/417,013, filed Apr. 2, 2009, Young et al.
U.S. Appl. No. 12/417,015, filed Apr. 2, 2009, Young.
U.S. Appl. No. 12/417,018, filed Apr. 2, 2009, Young et al.
U.S. Appl. No. 12/417,020, filed Apr. 2, 2009, Gaide et al.
U.S. Appl. No. 12/417,023, filed Apr. 2, 2009, Gaide et al.
U.S. Appl. No. 12/417,024, filed Apr. 2, 2009, Gaide et al.
U.S. Appl. No. 12/417,033, filed Apr. 2, 2009, Gaide et al.
U.S. Appl. No. 12/417,036, filed Apr. 2, 2009, Gaide et al.
U.S. Appl. No. 12/417,040, filed Apr. 2, 2009, Gaide et al.
U.S. Appl. No. 12/417,043, filed Apr. 2, 2009, Gaide et al.
U.S. Appl. No. 12/417,046, filed Apr. 2, 2009, Young et al.
U.S. Appl. No. 12/417,048, filed Apr. 2, 2009, Young et al.
U.S. Appl. No. 12/417,051, filed Apr. 2, 2009, Young et al.
U.S. Appl. No. 12/417,054, filed Apr. 2, 2009, Young et al.
U.S. Appl. No. 12/417,057, filed Apr. 2, 2009, Young et al.
Achronix Semiconductor Corp.,Introduction to Achronix FPGAs, WP001 Rev. 1.6, Aug. 7, 2008, pp. 1-7, available from Achronix Semiconductor Corp., San Jose, California, USA.
Achronix Semiconductor Corp.,Speedster FPGA Family, PB001 v3.5, copyright 2008, pp. 1-2, available from Achronix Semiconductor Corp., San Jose, California, USA.
Ye, A. et al., “Measuring and utilising the correlation between signal connectivity and signal positioning for FPGAs containing multi-bit building blocks,”IEE Proc.-Comput. Digit. Tech., May 2006, pp. 146-156, vol. 153, No. 3.
Ye, Andy et al., “Using Bus-Based Connections to Improve Field-Programmable Gate-Array Density for Implementing Datapath Circuits,”IEEE Transactions on Very Large Scale Integrations(VLSI)Systems, May 2006, pp. 462-473, vol. 14, No. 5.
Borriello, G. et al.; “The Triptych FPGA Architecture”; IEEE Transactions on Very Large Scale Integration (VLSI) Systems; vol. 3, No. 4; Dec. 1990; Copyright 1995 IEEE; pp. 491-501.
Sparso, J.; “Asynchronous Circuit Design—A Tutorial”; Copyright 2006 Jens Sparso; Technical University of Denmark; pp. 1-179.
Huang, Randy; “Hardware-Assisted Fast Routing for Runtime Reconfigurable Computing”; A dissertation submitted in partial satisfaction . . . University of California, Berkeley; Fall 2004; pp. 1-43.
Teifel, John et al.; “Highly Pipelined Asynchronous FPGAs”; FPGA '04; Feb. 22-24, 2004; Copyright 2004 ACM; pp. 133-142.
Hauser, John; “The Garp Architecture”; University of California at Berkeley; ;Oct. 1997; pp. 1-56.
Payne, R.; “Asynchronous FPGA Architecture”; Copyright IEE, 1996; IEE Proceedings online No. 19960655; Dec. 13, 1996; pp. 282286.
Martin, Alain et al.; “The Design of an Asynchronous Microprocessor”; Proc. Decennial Caltech Conference on VLSI; Mar. 20-22, 1989; pp. 1-23.
Hauck, Scott et al.; “Montage: An FPGA for Synchronous and Asynchronous Circuits”; Field-Programmable Gate Arrays: Architecture and Tools for Rapid Prototyping; 1993; pp. 44-51.
Hauck, Scott, et al.; “An FPGA for Implementing Asynchronous Circuits”; IEEE Design and Test of Computers; vol. II, No. 3; Fall, 1994; pp. 60-69.
Hauck, Scott; “Asynchronous Design Methodologies: An Overview”; Proceedings of the IEEE; vol. 83, No. 1; Jan. 1995; pp. 69-93.
From Wikipedia, the free Encyclopedia; “C-element”; downloaded from http://en.wikipedia.org/wiki/C-element, Jul. 17, 2008; pp. 1-2.
Tsu, William et al.; “High-Speed, Hierarchical Synchronous Reconfigurable Array”; FPGA 99 Monterey CA; Copyright ACM 1999; pp. 125-134.
Xilinx, Inc.; U.S. Appl. No. 12/174,905 by Young, filed Jul. 17, 2008.
Xilinx, Inc.; U.S. Appl. No. 12/174,926 by Young, filed Jul. 17, 2008.
Xilinx, Inc.; U.S. Appl. No. 12/174,945 by Young, filed Jul. 17, 2008.
Xilinx, Inc.; U.S. Appl. No. 12/174,956 by Young, filed Jul. 17, 2008.

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