Methods of incorporating germanium within CMOS process

Details Methods of incorporating germanium within CMOS process Methods of incorporating germanium within CMOS process

2005-05-03

2005-05-03

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Formation of semiconductive active region on any substrate

On insulating substrate or layer

C438S958000

Reexamination Certificate

active

06887773

ABSTRACT:
Methods for deposition of a Ge layer during a CMOS process on a monolithic device are disclosed. The insertion of the Ge layer enables the conversion of light to electrical signals easily. As a result of this method, standard metals can be attached directly to the Ge in completing an electrical circuit. Vias can also be used to connect to the Ge layer. In a first aspect of the invention, a method comprises the step of incorporating the deposition of Ge at multiple temperatures in a standard CMOS process. In a second aspect of the invention, a method comprises the step of incorporating the deposition of poly-Ge growth in a standard CMOS process.

REFERENCES:
patent: 5861059 (1999-01-01), Suzuki
patent: 6171973 (2001-01-01), Schiavone et al.
patent: 6271144 (2001-08-01), Monget et al.
patent: 6537894 (2003-03-01), Skotnicki et al.

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