Methods of implementing scalable routing matrices for...

Details Methods of implementing scalable routing matrices for... Methods of implementing scalable routing matrices for...

2006-01-24

2006-01-24

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000, C716S030000, C716S030000

Reexamination Certificate

active

06989690

ABSTRACT:
Methods of implementing routing matrices for programmable logic devices (PLDs). Each method includes generating a seed matrix, a distribution matrix, adjustment values for the distribution matrix, and a routing matrix pattern. The seed matrix and distribution matrix are implemented according to a set of rules that define valid matrices. The routing matrix is then implemented by applying the routing matrix pattern to provide programmable interconnections between input and output terminals of the routing matrix. Each signal value in the routing matrix pattern corresponds to one of the input terminals, and each row of signal values in the routing matrix pattern corresponds to a set of the input terminals programmably coupled to a different one of the output terminals. By adding additional columns of sub-matrices to an existing distribution matrix, an existing routing matrix can also be expanded to accommodate a larger number of input signals.

REFERENCES:
patent: 5671432 (1997-09-01), Bertolet et al.
patent: 6594816 (2003-07-01), Hauck

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