Methods of identifying defects in an array of memory cells...

Details Methods of identifying defects in an array of memory cells... Methods of identifying defects in an array of memory cells...

2000-06-01

2001-04-03

Nelms, David (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S190000

Reexamination Certificate

active

06212114

ABSTRACT:

TECHNICAL FIELD
This invention pertains to methods of identifying defects in arrays of memory cells, and to related integrated circuitry.
BACKGROUND OF THE INVENTION
Fabrication of memory array circuitry involves a number of complex processing steps. It is highly desirable to test such circuitry for defects prior to providing a finished product for the customer. Undetected defects can be highly problematic in finished integrated circuitry because of the increased likelihood of erroneous output data.
To assist in understanding the various embodiments of the invention described below, some background information is provided in connection with
FIGS. 1 and 2
.
FIG. 1
shows an exemplary portion of memory array circuitry generally at
20
. Circuitry
20
comprises a semiconductive substrate
22
having a plurality of field oxide regions
24
formed thereover. Individual diffusion regions
26
are provided within substrate
22
. A plurality of word lines
28
are provided over the substrate and typically include a polysilicon layer
30
, a silicide layer
32
, overlying insulative cap
34
, and sidewall spacers
36
. Individual capacitor constructions are provided at
38
and include conductive storage nodes
40
, a dielectric layer
42
, e.g. an ONO layer, and a cell plate layer
44
. A bit line
46
is disposed over capacitors
38
and is operably connected with its associated diffusion region
26
through a bit line contact
48
. This type of memory circuitry is known as bit line-over-capacitor circuitry. One common failure or defect which can occur in this type of circuitry is for the bit line
46
to become short circuited to cell plate layer
44
. Such can occur, for example, in an area designated at A when a sufficient voltage causes the dielectric layer separatingthese components to break down in a manner which is similar to that of an antifuse.
Another type of memory array circuitry is shown in
FIG. 2
generally at
20
a
. Like numerals from the above-described memory circuitry have been utilized where appropriate with differences being indicated by the suffix “a”. This ,type of memory array circuitry is known as capacitor-over-bit line circuitry. As shown, individual capacitors
38
a
are disposed over bit line
46
a
. A typical failure or defect which can occur in this type of memory array circuitry is a word line-to-bit line short circuit. Specifically, such can occur in the area designated at B.
The defects of concern might not inherently be created or perceptible during normal operation, but potentially can exist or can be created later during so-called burn-in operations. This could result from a less than desirable spacing between the respective components which can become short circuited together. In the past, methods have evolved for stress testing such circuitry, but such methods have fallen short of providing either or both of time savings or wafer real estate savings.
One method which has been utilized to achieve defect identification involves the fabrication of a plurality of dedicated bus lines which are configured to provide test voltages across the memory array. For example, and with respect to
FIG. 1
where defects can occur if bit line
46
becomes short circuited to cell plate
44
, these plural dedicated bus lines have been utilized to force a voltage differential between the bit line and the cell plate so as to cause a breakdown in possibly defective insulative material separating the two. One primary disadvantage of this method is that it requires several dedicated bus lines to be formed over the semiconductor wafer which supports the memory circuitry. This is problematic from the standpoint of undesirably consuming wafer real estate, i.e. it undesirably increases the die size which decreases the die per wafer, which would otherwise be available to support additional memory circuitry.
Another method which has been utilized in the past involves utilizing circuitry which already exists on the substrate. Specifically, and with respect to
FIG. 1
, a voltage differential can be developed between cell plate
44
and bit line
46
by taking one of the two to a high potential, and the other of the two to a low potential. Essentially problematic with this approach with respect to memory circuitry, and in particular DRAM circuitry which uses a so-called complimentary bit line or digit line construction, is that the bit lines/digit lines are hard wired so that when one goes high, the other goes low. Accordingly, to adequately test all of the memory cells comprising a memory array, additional processing steps must be taken because of the complementary behavior of the digit line pairs. Needless to say, these additional processing steps consume valuable processing time and reduce throughput. For example, processing times can be increased from 2- to 8-times the processing time than if the entire array were able to be tested at once. Specifically, in one type of architecture which is discussed below in much more detail, the array utilizes complementary digit line pairs which are configured to assume complementary states. The digit line pairs typically extend from different array blocks. Because of the complementary nature of the digit line pairs, when one array block is tested by placing one of the digit lines of a digit line pair at a particular potential, the other digit line is not or cannot be tested. Hence, the array blocks must be separately tested.
Accordingly, this invention arose out of concerns associated with providing improved methods of testing integrated circuitry, and in particular memory array circuitry for defects. In particular, this invention arose out of concerns associated with providing testing procedures which save time, and related integrated circuitry which does not consume a meaningful amount of wafer real estate.
SUMMARY OF THE INVENTION
Methods of identifying defects in an array of memory cells and related integrated circuitry are described. In one embodiment, an array of memory cells is provided having a plurality of complementary digit line pairs. The digit line pairs comprise individual digit lines D
0
n
, D
0
n
*, where n>1. The complementary digit line pairs are configured to be placed into different states during sensing operations of the array. A defect-identifying signal is applied to the array by driving both digit lines of at least one digit line pair to a common test state, and the cell plate to another different test state with the use of only one dedicated bus line.
In another embodiment, a pair of memory cells is provided each having an access transistor and a capacitor. The capacitor has a cell plate. Write circuitry is operably coupled with the pair of memory cells through respective individual input lines. The write circuitry is configured to write data into the memory cells. A defect-identifying condition is imposed on the array by placing the cell plate into a first test state, and, using the write circuitry, placing both of the input lines into a common second test state which is different from the first test state.


REFERENCES:
patent: 5848018 (1998-12-01), McClure
patent: 6094388 (2000-07-01), Cowles

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