Methods of forming vertical field effect transistors,...

Details Methods of forming vertical field effect transistors,... Methods of forming vertical field effect transistors,...

2011-03-22

2011-03-22

Monbleau, Davienne (Department: 2893)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S269000, C257S328000, C257S329000, C257SE21409, C257SE29345

Reexamination Certificate

active

07910971

ABSTRACT:
A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the opening base are lined with masking material. A semiconductive material pillar is epitaxially grown to within the opening adjacent the masking material from the semiconductor material at the opening base. At least some of the masking material is removed from the opening. A gate dielectric is formed radially about the pillar. Conductive gate material is formed radially about the gate dielectric. An upper portion of the pillar is formed to comprise one source/drain region of the vertical transistor. Semiconductive material of the pillar received below the upper portion is formed to comprise a channel region of the vertical transistor. Semiconductor material adjacent the opening is formed to comprise another source/drain region of the vertical transistor. Other aspects and implementations are contemplated.

REFERENCES:
patent: 7176089 (2007-02-01), Furukawa et al.
patent: 7285812 (2007-10-01), Tang et al.
patent: 2006/0046392 (2006-03-01), Manning et al.
patent: 60160169 (1985-08-01), None
patent: 7254647 (1995-10-01), None

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