Methods of forming trench isolation regions using preferred...

Details Methods of forming trench isolation regions using preferred... Methods of forming trench isolation regions using preferred...

1999-05-06

2001-02-13

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S296000, C438S424000

Reexamination Certificate

active

06187651

ABSTRACT:

RELATED APPLICATION
This application is related to Korean Application No. 98-16334, filed May 5, 1998, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
This invention relates to integrated circuit device fabrication methods and, more particularly, to methods of forming field oxide isolation regions in semiconductor substrates.
BACKGROUND OF THE INVENTION
Improved active device isolation techniques are required in order to facilitate ongoing attempts to increase integration density in integrated circuit devices by designing devices having reduced unit cell size. Conventional device isolation techniques include local oxidation of silicon (LOCOS) and shallow trench isolation (STI) techniques, for example. Such device isolation techniques are disclosed in U.S. Pat. Nos. 5,677,234, 5,750,433, 5,753,562, 5,837,595, 5,858,842 and 5,885,883.
But, such techniques as LOCOS may not be appropriate for current high integration devices because they typically result in the formation of isolation regions having bird's beak oxide extensions which may consume relatively large amounts of area and thereby impede attempts for higher integration levels. To address this and other problems, STI techniques have been developed. One such technique is illustrated by
FIGS. 1A-1E
. In particular,
FIG. 1A
illustrates the steps of forming a pad oxide layer
3
, a pad nitride layer
4
, a high temperature oxide (HTO) layer
5
and an anti-reflective layer
6
on a semiconductor substrate
2
. A photoresist layer
10
is then patterned on the anti-reflective layer
6
. A trench mask
8
is then formed by performing an etching step using the patterned photoresist layer
10
as an etching mask. As illustrated by
FIG. 1B
, another etching step is then performed to define a trench
12
in the substrate
2
, using the trench mask
8
as a etching mask. During the etching step, the anti-reflective layer
6
may also be removed.
Referring now to
FIG. 1C
, a thermal oxide layer
14
is then formed in the trench to remove etching damage. A trench isolation layer comprising an undoped silicate glass (USG) layer
15
and a PE-TEOS oxide layer
16
(for reducing stress in the USG layer), is then formed to fill the trench
12
. As illustrated by
FIG. 1D
, a planarization step (e.g., CMP) is then performed, using the pad nitride layer
4
as an etch stop layer. Then, as illustrated by
FIG. 1E
, the pad nitride layer
4
and pad oxide layer
3
are sequentially removed to define a trench isolation region
18
.
Unfortunately, because the substrate
2
may have a substantially different coefficient of thermal expansion than the USG layer
15
in the trench
12
, substantial stresses may develop in the substrate
2
during back-end processing. These stresses may adversely influence the device characteristics of active devices formed in active regions adjacent the trench isolation region
18
. The subsequent formation of an oxide layer on the active regions (e.g., gate oxide layers) may also act to increase the degree of stress in the substrate
2
, due to volume expansion in the trench isolation region
18
. Grain dislocation defects may also be generated at the bottom corners and sidewalls of the trench in response to the volume expansion. Such defects may lead to increases in junction leakage currents in adjacent active devices, and decreases in reliability and yield.
Thus, notwithstanding the above described methods, there continues to be a need for improved methods of forming field oxide isolation regions.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved methods of forming field oxide isolation regions.
It is another object of the present invention to provide methods of forming field oxide isolation regions having reduced susceptibility to void defects therein.
It is still another object of the present invention to provide methods of forming trench isolation regions having low stress characteristics.
These and other objects, advantages and features of the present invention are provided by methods of forming trench isolation regions that include the steps of forming a trench in a semiconductor substrate and lining the trench with a first electrically insulating layer. A stress-relief nitride layer is then formed on the first electrically insulating layer, opposite sidewalls of the trench. The trench is then filled with a second electrically insulating layer. The second electrically insulating layer is then planarized. This is followed by the steps of etching the stress-relief nitride layer and then forming a third electrically insulating layer on the planarized second electrically insulating layer and on the stress-relief nitride layer. According to a preferred aspect of the present invention, the step of forming the trench is preceded by the step of forming a patterned pad nitride layer on the semiconductor substrate. The pad nitride layer may be used as a mask when etching the substrate to define the trench. The step of planarizing the second electrically insulating layer may also comprise the step of planarizing the second electrically insulating layer using the patterned pad nitride layer as an etch stop. Furthermore, the step of etching the stress-relief nitride layer may comprise etching the patterned pad nitride layer to expose sidewalls of the second electrically insulating layer. The step of forming a third electrically insulating layer may also comprise forming a high temperature oxide layer on the exposed sidewalls of the second electrically insulating layer, and may be followed by the step of etching the second and third electrically insulating layers simultaneously to define a trench isolation region in the trench. According to other preferred aspects of the present invention, the stress-relief nitride layer may comprise Si
4
N
4
and the step of filling the trench with a second electrically insulating layer may comprise filling the trench with an undoped silicate glass layer. The step of planarizing the second electrically insulating layer may also be preceded by the step of annealing the undoped silicate glass layer to increase its density.


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