Methods of forming trench isolation regions having conductive sh

Details Methods of forming trench isolation regions having conductive sh Methods of forming trench isolation regions having conductive sh

1999-06-09

2000-10-17

Smith, Matthew

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438435, 438221, H01L 2176, H01L 218238

Patent

active

061331163

ABSTRACT:
Narrow-channel effect free DRAM cell transistor structure for submicron isolation pitch DRAMs having lowed-doped substrate and active width-independent threshold voltage by employing conductive shield in the shallow trench isolation(STI). The resulting cell transistor structure is highly immune to parasitic E-field penetration from the gate and neighbouring storage node junctions via STI and will be very appropriate for Gbit scale DRAM technology. The conductive shield is biased with the negative voltage in order to minimize the sidewall depletion in the substrate.

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Search Report, GB 9913674.9, Sep. 22, 1999.

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