Methods of forming trench isolation regions having...

Details Methods of forming trench isolation regions having... Methods of forming trench isolation regions having...

1999-10-08

2001-06-26

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S221000, C438S296000, C438S435000, C438S439000

Reexamination Certificate

active

06251746

ABSTRACT:

RELATED APPLICATION
This application is related to Korean Application No. 98-42300, filed Oct. 9, 1998, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
This invention relates to methods of forming integrated circuit devices, and more particularly to methods of forming electrical isolation regions in semiconductor substrates.
BACKGROUND OF THE INVENTION
Trench isolation techniques have been considered as alternatives to local oxidation of silicon (LOCOS) isolation techniques because trench isolation techniques provide fully recessed oxides, may be planarized, do not result in the formation of bird's beaks oxide extensions and typically do not suffer from field oxide thinning effects. Such trench isolation techniques are more fully described in U.S. Pat. No. 5,750,433 to Jo entitled “Methods of Forming Electrically Isolated Active Region Pedestals Using Trench-Based Isolation Techniques”, U.S. Pat. No. 5,753,562 to Kim entitled “Methods of Forming Semiconductor Devices In Substrates Having Inverted-Trench Isolation Regions Therein”, and U.S. Pat. No. 5,858,842 to Park entitled “Methods of Forming Combined Trench and Locos-Based Electrical Isolation Regions In Semiconductor Substrates, all assigned to the present assignee, the disclosures of which are hereby incorporated herein by reference.
Unfortunately, the performance of thermal oxidation steps when forming trench isolation regions may cause volume expansion defects and dislocations to form adjacent the sidewalls and corners of the trenches as migrating oxygen reacts with the silicon at the trench sidewall interfaces. As will be understood by those skilled in the art, these defects and dislocations can degrade the electrical characteristics of devices formed in active regions which extend adjacent the trench isolation regions.
To address these limitations associated with conventional trench isolation techniques, attempts have been made to add stress-relieving liners (e.g., ON and ONO liners) to the sidewalls and bottoms of trenches. Such attempts are disclosed in U.S. Pat. Nos. 4,631,803, 5,189,501, 5,190,889 and 5,206,182. Unfortunately, conventional processing techniques may cause removal of the stress relieving lining material and result in the formation of voids which can degrade the electrical isolation characteristics of the trench isolation regions. For example, as illustrated by
FIGS. 1A-1B
, conventional processing techniques may cause a trench nitride layer
10
to become recessed and the formation of a void as illustrated by highlighted region
14
.
In particular,
FIG. 1A
illustrates a trench isolation region at an intermediate stage of processing. This trench isolation region may be formed by thermally oxidizing a face of a substrate
1
to define a pad oxide layer
2
and then depositing a silicon nitride masking layer
4
on the pad oxide layer
2
. The silicon nitride masking layer
4
may then be patterned using conventional photolithographically defined etching steps. The silicon nitride masking layer
4
may then be used as an etching mask during the formation of a trench
6
in the substrate
1
. The sidewalls and bottom of the trench
6
may then be thermally oxidized to define a trench oxide layer
8
. A trench nitride layer
10
may then be deposited on the trench oxide layer
8
and on the silicon nitride masking layer
4
. The trench may then be filled with an electrically insulating material
12
(e.g., USG). A planarization step may then be performed, using the silicon nitride masking layer
4
as a planarization-stop. Then, as illustrated by
FIG. 1B
, an etching step can be performed using a wet etchant (e.g., phosphoric acid) to remove the silicon nitride masking layer
4
. Unfortunately, this etching step may also cause the trench nitride layer
10
to become recessed, as illustrated. The extent of this recession may be reduced by using thinner trench nitride layers
10
, however, the use of thinner trench nitride layers
10
may reduce the stress-relieving benefits provided by the trench nitride layers
10
. Such techniques to use thinner trench nitride layers
10
are more fully disclosed in U.S. Pat. No. 5,447,884.
Thus, notwithstanding the above-described methods of forming trench isolation regions, there continues to be a need for improved methods of forming trench isolation regions.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved methods of forming trench isolation regions in semiconductor substrates.
It is another object of the present invention to provide methods of forming trench isolation regions that inhibit the formation of dislocations and stresses in portions of a semiconductor substrate extending adjacent the trench isolation regions.
It is still another object of the present invention to provide methods of forming integrated circuit substrates having active devices therein that are not adversely influenced by defects within adjacent trench isolation regions.
These and other objects, advantages and features of the present invention are provided by methods of forming trench isolation regions that include the steps of forming a trench masking layer comprising a first material (e.g., polysilicon) on a semiconductor substrate and then etching a trench in the semiconductor substrate, using the trench masking layer as etching mask. A trench nitride layer comprising a second material different from the first material is then formed on a sidewall of the trench and on a sidewall of the trench masking layer. The trench is then filled with a trench insulating material (e.g., USG). The trench masking layer is then removed by selectively etching the trench masking layer with an etchant that selectively etches the first material at a higher rate than the second material. This step of removing the trench masking layer results in exposure of a protruding portion of the trench nitride layer but does not cause the trench nitride layer to become recessed. The trench insulating material and the trench nitride layer are then etched back to define the trench isolation region.
According to one aspect of the present invention, the step of forming a trench nitride layer is preceded by the step of forming a trench oxide layer on the sidewall of the trench and on a sidewall of the trench masking layer. In particular, the trench oxide layer is formed on a sidewall of the trench masking layer by thermally oxidizing the sidewall of the trench masking layer. The step of etching back the trench insulating material also preferably comprises the step of etching the trench insulating material and the trench oxide layer simultaneously, to expose a protruding portion of the trench nitride layer and then etching the protruding portion of the trench nitride layer. The step of forming a trench masking layer is also preferably preceded by the step of forming a pad oxide layer on a surface of the semiconductor substrate. The step of removing the trench masking layer is also preferably performed by exposing the trench masking layer to an etching solution comprising HNO
3
, CH
3
COOH, HF and deionized water.
To further reduce stress within the semiconductor substrate, the trench nitride layer preferably comprises a silicon-rich nitride layer as Si
3+&agr;
N
4
, where &agr;>0, having a thickness in a range between about 70 Å and 300 Å.
According to another embodiment of the present invention, a method of forming a trench isolation region comprises the steps of forming a first trench masking layer comprising polysilicon on a semiconductor substrate and forming a second trench masking layer comprising silicon nitride on the first trench masking layer. A trench is then etched into the semiconductor substrate, using the first trench masking layer as etching mask. A trench nitride layer is then formed on a sidewall of the trench and on sidewalls of the first and second trench masking layers. The trench is then filled with a trench insulating material (e.g., USG and PE-TEOS). The second trench masking layer is the

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