Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate
Reexamination Certificate
2011-08-02
2011-08-02
Chen, Jack (Department: 2893)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
C438S589000, C257SE21090
Reexamination Certificate
active
07989322
ABSTRACT:
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.
REFERENCES:
patent: 4820654 (1989-04-01), Lee
patent: 4993143 (1991-02-01), Sidner et al.
patent: 5021843 (1991-06-01), Ohmi
patent: 5281840 (1994-01-01), Sarma
patent: 5374329 (1994-12-01), Miyawaki
patent: 5405802 (1995-04-01), Yamagata et al.
patent: 5453394 (1995-09-01), Yonehara et al.
patent: 5670411 (1997-09-01), Yonehara et al.
patent: 5767020 (1998-06-01), Sakaguchi et al.
patent: 5773355 (1998-06-01), Inoue et al.
patent: 5841171 (1998-11-01), Iwamatsu et al.
patent: 5849627 (1998-12-01), Linn et al.
patent: 5882532 (1999-03-01), Field et al.
patent: 5910672 (1999-06-01), Iwamatsu et al.
patent: 5923046 (1999-07-01), Tezuka et al.
patent: 6010921 (2000-01-01), Soutome
patent: 6037634 (2000-03-01), Akiyama
patent: 6048411 (2000-04-01), Henley et al.
patent: 6071783 (2000-06-01), Liang et al.
patent: 6091076 (2000-07-01), Deleonibus
patent: 6093623 (2000-07-01), Forbes
patent: 6177333 (2001-01-01), Rhodes
patent: 6204524 (2001-03-01), Rhodes
patent: 6215155 (2001-04-01), Wollesen
patent: 6245636 (2001-06-01), Maszara
patent: 6255731 (2001-07-01), Ohmi et al.
patent: 6265327 (2001-07-01), Kobayashi et al.
patent: 6268630 (2001-07-01), Schwank et al.
patent: 6313014 (2001-11-01), Sakaguchi et al.
patent: 6340829 (2002-01-01), Hirano et al.
patent: 6346729 (2002-02-01), Liang et al.
patent: 6350703 (2002-02-01), Sakaguchi et al.
patent: 6358791 (2002-03-01), Hsu et al.
patent: 6403485 (2002-06-01), Quek et al.
patent: 6410938 (2002-06-01), Xiang
patent: 6433401 (2002-08-01), Clark et al.
patent: 6509613 (2003-01-01), En et al.
patent: 6512244 (2003-01-01), Ju et al.
patent: 6531375 (2003-03-01), Giewont et al.
patent: 6534380 (2003-03-01), Yamauchi et al.
patent: 6541861 (2003-04-01), Higashi et al.
patent: 6552396 (2003-04-01), Bryant et al.
patent: 6552496 (2003-04-01), Yamazaki
patent: 6610615 (2003-08-01), McFadden et al.
patent: 6627549 (2003-09-01), Juengling
patent: 6642579 (2003-11-01), Fung
patent: 6649959 (2003-11-01), Hsu et al.
patent: 6661065 (2003-12-01), Kunikiyo
patent: 6664146 (2003-12-01), Yu
patent: 6670257 (2003-12-01), Barlocchi et al.
patent: 6680243 (2004-01-01), Kamath et al.
patent: 6683364 (2004-01-01), Oh et al.
patent: 6808954 (2004-10-01), Ma et al.
patent: 6870235 (2005-03-01), Absteiter et al.
patent: 7023051 (2006-04-01), Forbes
patent: 7029989 (2006-04-01), Kim et al.
patent: 7153753 (2006-12-01), Forbes
patent: 7229895 (2007-06-01), Wells
patent: 7378704 (2008-05-01), Parekh
patent: 7393789 (2008-07-01), Abatchev et al.
patent: 7416943 (2008-08-01), Figura et al.
patent: 7498265 (2009-03-01), Wells et al.
patent: 7557002 (2009-07-01), Wells et al.
patent: 7572572 (2009-08-01), Wells
patent: 7601608 (2009-10-01), Wells
patent: 7625776 (2009-12-01), Wells et al.
patent: 7628932 (2009-12-01), Lee et al.
patent: 7682944 (2010-03-01), Brandes et al.
patent: 7709341 (2010-05-01), Fucsko et al.
patent: 2001/0020722 (2001-09-01), Yang
patent: 2002/0011670 (2002-01-01), Higashi et al.
patent: 2002/0034844 (2002-03-01), Hsu et al.
patent: 2002/0048844 (2002-04-01), Sakaguchi
patent: 2002/0070454 (2002-06-01), Yasukawa
patent: 2002/0090816 (2002-07-01), Ashby et al.
patent: 2002/0134503 (2002-09-01), Hussinger et al.
patent: 2003/0085424 (2003-05-01), Bryant et al.
patent: 2004/0124446 (2004-07-01), Borger et al.
patent: 2004/0183078 (2004-09-01), Wang
patent: 2005/0139952 (2005-06-01), Koh
patent: 2005/0176222 (2005-08-01), Ogura
patent: 2006/0043515 (2006-03-01), Ford
patent: 2006/0207972 (2006-09-01), D'arrigo et al.
patent: 2007/0032092 (2007-02-01), Shibata et al.
patent: 2007/0249138 (2007-10-01), Li et al.
patent: 2008/0044979 (2008-02-01), Wells
patent: 2008/0048196 (2008-02-01), Strittmatter et al.
patent: 2008/0085587 (2008-04-01), Wells et al.
patent: 2008/0113483 (2008-05-01), Wells
patent: 2008/0173964 (2008-07-01), Akram
patent: 2008/0187463 (2008-08-01), Wells
patent: 2008/0188019 (2008-08-01), Wells
patent: 2008/0188051 (2008-08-01), Wells
patent: 2008/0261349 (2008-10-01), Abatchev et al.
patent: 2009/0236666 (2009-09-01), Wells et al.
patent: 10 2005 010 821 (2006-09-01), None
patent: 1184897 (2002-03-01), None
patent: 1427011 (2004-06-01), None
patent: 2007/074027 (2007-07-01), None
patent: PCT/US2007/016150 (2007-07-01), None
patent: PCT/US2008/001126 (2008-01-01), None
Bashir et al.,Characterization of sidewall defects in selective epitaxial growth of silicon, J. Vac. Sci. Technol. B, vol. 13, No. 3, pp. 923-927 (May/Jun. 1995).
Bernstein et al. ,Chapter 3: SOI Device Electrical Properties, § 3.4 Floating Body Effects, SOI Circuit Design Concepts, pp. 34-53 (Kluwer Academic Publishers, pre-Aug. 2001).
Hammad et al.,The Pseudo-Two-Dimensional Approach to Model the Drain Section in SIO MOSFETs, IEEE Transactions on Electron Devices, vol. 48, No. 2, pp. 386-387 (Feb. 2001).
Sivagnaname et al.,Stand-by Current in PD-SOI Pseudo-nMOS Circuits, IEEE, pp. 95-96 (2003).
Wang et al.,Achieving Low Junction Capacitance on Bulk SI MOSFET Using SDOI Process, Micron Technology, Inc., 12 pages (pre-2004).
R. Bashir et al.,Reduction of sidewall defect induced leakage currents by the use of nitrided field oxides in silicon selective epitaxial growth isolation . . ., J. Vac. Sci. Technol. B , vol. 18, No. 2, pp. 695-699 (Mar./Apr. 2000).
E. A. Fitzgerald et al.,Dislocation Engineering in Strained MOS Materials, IEEE, 4 pages (2005).
Abstract: S. H. Parng et al.,DNA Extraction With Parallel Electrodes on Microfluidic System, Technical Proceedings of the 2006 NSTI Nanotechnology Conference and Trade Show, vol. 2, Chapter 8, 1 page (2006).
T. Simonite,Nanopore will make for speedy DNA sequencing, NewScientistTech, 3 pages (Apr. 10, 2006).
K. Terada et al.,A New DRAM Cell With a Transistor on a Lateral Epitaxial Silicon Layer(TOLE Cell), IEEE Transactions on Electron Devices, vol. 37, No. 9, pp. 2052-2057 (Sep. 9, 1990).
K. Wang et al.,Nanofluidic channels fabrication and manipulation of DNA molecules, IEEE Proc.-Nanobiotechnol., vol. 153, No. 1, pp. 11-15 (Feb. 2006).
Mendis et al.,CMOS Active Pixel Image Sensor, IEEE Transactions on Electron Devices, Fol. 41, No. 3, pp. 452-453 (Mar. 1994).
Nixon et al.,256×256 CMOS Active Pixel Sensor Camera-on-a-Chip, IEEE Journal of Solid-State Circuits, vol. 31, No. 12, pp. 2046-2050 (Dec. 1996).
U.S. Appl. No. 11/657,013, filed Jan. 24, 2007, Akram.
WO, PCT/US07/016150, Apr. 9, 2008, Written Opinion.
WO, PCT/US07/016150, Apr. 9, 2008, Search Report.
Jurczak et al., “Silicon-on-Nothing (SON)—an Innovative Process for Advanced CMOS,” IEEE Transactions on Electron Devices, vol. 47, No. 11 (Nov. 2000).
L. Jastrzebski et al., “Device Characterization on Monocrystalline Silicon Grown Over SiO2, by the ELO (Epitaxial Lateral Overgrowth) Process,” IEEE Electron Device Letters, vol. EDL-4, No. 2 (Feb. 1983).
Sato et al., “SON (Silicon on Nothing) MOSFET using ESS (Empty Space in Silicon) technique for SoC applications,” IEEE (2001).
Terada et al., “A New DRAM Cell with a Transistor on a Lateral Epitaxial Silicon Layer (TOLE Cell),” IEEE Transactions on Electron Devices, vol. 37, No. 9 (Sep. 1990).
Yeo et al., “80 nm 512M DRAM with Enhanced Data Retention Time Using Partially-Insulated Cell Array Transistor (PiCAT),” 2004 Symposium on VLSI Technology, Digest of Technical Papers, pp. 30-31 (2004).
Yeo et al., “A Partially Insulated Field-Effect Transistor (PiFET) as a Candidate for Scaled Transistors,” IEEE Electron Device Letters, vol. 25, No. 6 (Jun. 2004).
PCT/US2008/001126, dated Nov. 12, 2008, Invitation to Pay Addl Fees.
PCT/US2008/001126, dated Feb. 2, 2009, Search Repo
Chen Jack
Micro)n Technology, Inc.
Wells St. John P.S.
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