Methods of forming through-wafer interconnects and...

Details Methods of forming through-wafer interconnects and... Methods of forming through-wafer interconnects and...

2005-08-05

2008-09-30

Sarkar, Asok K (Department: 2891)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C257SE21597

Reexamination Certificate

active

07429529

ABSTRACT:
Methods for forming conductive vias or through-wafer interconnects in semiconductor substrates and resulting through-wafer interconnect structures are disclosed. In one embodiment of the present invention, a method of forming a through-wafer interconnect structure includes the acts of forming an aperture in a first surface of a substrate, depositing a first insulative or dielectric layer on an inner surface of the aperture, depositing an electrically conductive layer over the first dielectric layer, depositing a second insulative or dielectric layer on the inner surface of the aperture over the electrically conductive material, and exposing a portion of the electrically conductive layer through the second, opposing surface of the substrate. Semiconductor devices including through-wafer interconnects produced with the methods of the instant invention are also described.

REFERENCES:
patent: 4445978 (1984-05-01), Whartenby et al.
patent: 4806111 (1989-02-01), Nishi et al.
patent: 5063177 (1991-11-01), Geller et al.
patent: 5166097 (1992-11-01), Tanielian
patent: 5229647 (1993-07-01), Gnadinger
patent: 5236551 (1993-08-01), Pan
patent: 5269880 (1993-12-01), Jolly et al.
patent: 5380681 (1995-01-01), Hsu
patent: 5420520 (1995-05-01), Anschel et al.
patent: 5426072 (1995-06-01), Finnila
patent: 5438212 (1995-08-01), Okaniwa
patent: 5483741 (1996-01-01), Akram et al.
patent: 5495667 (1996-03-01), Farnworth et al.
patent: 5528080 (1996-06-01), Goldstein
patent: 5541525 (1996-07-01), Wood et al.
patent: 5559444 (1996-09-01), Farnworth et al.
patent: 5592736 (1997-01-01), Akram et al.
patent: 5607818 (1997-03-01), Akram et al.
patent: 5686317 (1997-11-01), Akram et al.
patent: 5796264 (1998-08-01), Farnworth et al.
patent: 5841196 (1998-11-01), Gupta et al.
patent: 5843844 (1998-12-01), Miyanaga
patent: 6013948 (2000-01-01), Akram et al.
patent: 6018196 (2000-01-01), Noddin
patent: 6022797 (2000-02-01), Ogasawara et al.
patent: 6054377 (2000-04-01), Filipiak et al.
patent: 6080664 (2000-06-01), Huang et al.
patent: 6110825 (2000-08-01), Mastromatteo et al.
patent: 6114240 (2000-09-01), Akram et al.
patent: 6214716 (2001-04-01), Akram
patent: 6221769 (2001-04-01), Dhong et al.
patent: 6355181 (2002-03-01), McQuarrie
patent: 6400172 (2002-06-01), Akram et al.
patent: 6410976 (2002-06-01), Ahn
patent: 6420209 (2002-07-01), Siniaguine
patent: 6458696 (2002-10-01), Gross
patent: 6479382 (2002-11-01), Naem
patent: 6541280 (2003-04-01), Kaushik et al.
patent: 6620731 (2003-09-01), Farnworth et al.
patent: 6667551 (2003-12-01), Hanaoka et al.
patent: 6716737 (2004-04-01), Plas et al.
patent: 6770923 (2004-08-01), Nguyen et al.
patent: 6809421 (2004-10-01), Hayasaka et al.
patent: 6821877 (2004-11-01), Han
patent: 6841883 (2005-01-01), Farnworth et al.
patent: 6846725 (2005-01-01), Nagarajan et al.
patent: 6979652 (2005-12-01), Khan et al.
patent: 7029937 (2006-04-01), Miyazawa
patent: 7135762 (2006-11-01), Yamaguchi
patent: 2002/0115290 (2002-08-01), Halahan et al.
patent: 2002/0148807 (2002-10-01), Zhao et al.
patent: 2004/0080040 (2004-04-01), Dotta et al.
patent: 2004/0217483 (2004-11-01), Hedler et al.
patent: 2005/0006768 (2005-01-01), Narahinthan et al.
patent: 2005/0106845 (2005-05-01), Halahan et al.
patent: 2005/0121768 (2005-06-01), Edelstein et al.
patent: 2005/0136568 (2005-06-01), Fukazawa
patent: 2005/0199973 (2005-09-01), Benzel et al.
patent: 0 926 723 (1997-11-01), None
International Search Report, dated Nov. 16, 2006 (4 pages).
Lee et al., Laser Created Silicon Vias for Stacking Dies in MCMs, EMT Symposium, 1991, Tampa, Florida, pp. 262, 263, 265.
Chu et al., Laser Micromachining of Through Via Interconnects in Active Die for 3-D Multichip Module, IEEE/CMPT Int'l EMT Symposium, 1995, pp. 120-126.

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