Methods of forming thin film transistors having lightly-doped dr

Details Methods of forming thin film transistors having lightly-doped dr Methods of forming thin film transistors having lightly-doped dr

1996-06-06

1997-12-02

Niebling, John

Fishing, trapping, and vermin destroying

437 41, 437 44, H01L 21265

Patent

active

056935463

ABSTRACT:
Methods of forming field effect transistors include the steps of forming a composite of layers including an amorphous silicon layer (a--Si), a silicon dioxide layer thereon and a silicon nitride layer on the silicon dioxide layer. A polycrystalline silicon conductive layer is then formed on the silicon nitride layer by depositing and patterning polycrystalline silicon. The polycrystalline silicon conductive layer is then oxidized using thermal oxidation techniques to form an oxide outerlayer. During this step, a portion of the polycrystalline silicon conductive layer will be consumed to define a gate electrode. Dopants of first conductivity type are then implanted into a top surface of the silicon nitride layer, using the oxide outerlayer and the gate electrode as a mask, to form relatively lightly doped preliminary source and drain regions in the amorphous silicon layer. The oxide outerlayer is then removed preferably using a buffered oxide etchant (BOE) solution which does not etch silicon nitride. Following this, dopants of first conductivity type are again implanted into the amorphous silicon layer, using the gate electrode as a mask. The second implantation step causes the formation of a field effect transistor having self-aligned source and drain regions, self-aligned lightly doped source and drain region extensions (LDS, LDD) and a channel region therebetween which has the same length as the gate electrode. By forming the channel region to have the same length as the gate electrode, improved device characteristics can be achieved.

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