Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-08-19
2001-09-04
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S679000, C438S685000, C438S688000, C438S681000, C438S672000
Reexamination Certificate
active
06284646
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit devices and, more particularly to metal layers for integrated circuit devices.
BACKGROUND OF THE INVENTION
In semiconductor integrated circuit devices, alloys or multi-layered metallizations are used to provide metal interconnections between circuits of the integrated circuit devices. In particular, aluminum or an aluminum alloy is often used to provide the metal interconnections. A layer of aluminum or an aluminum alloy can be deposited on an insulating layer (such as a silicon oxide layer) of the integrated circuit device, and the aluminum or aluminum alloy layer can be deposited into openings such as contact holes, trenches, vias, and/or grooves in the insulating layer. The aluminum or aluminum alloy layer can then be patterned to provide metal interconnection lines of the insulating layer with interconnections to other layers through the openings in the insulating layer. Aluminum has been widely used because aluminum has a good electrical conductivity compared with other metals and low contact resistance with respect to silicon.
In the manufacture of integrated circuit (IC) devices, metal layers such as the aluminum or aluminum alloy layers discussed above have often be formed using physical vapor deposition (PVD) techniques such as sputtering. With the advent of very large scale integration (VLSI) integrated circuit devices, however, the diameters of openings within which the metal layers are deposited is being reduced and the aspect ratios of these openings is increasing. In other words, a ratio of the depth of these openings to the diameter of these openings is increasing. It may thus be difficult to form a metal layer by sputtering and also provide a uniform distribution of the metal layer around high aspect ratio openings (such as contact holes having submicron diameters) in the insulating layer due to shadow effects caused by substrate morphologies. Accordingly, it may be difficult to use physical vapor deposition techniques to form metal interconnection layers for very large scale integration (VLSI) and ultra large scale integration (ULSI) integrated circuit devices.
Chemical vapor deposition (CVD) techniques can be used to form metal interconnection layers with improved step coverage when compared to metal layers formed using physical vapor deposition techniques. In particular, it is possible to form and grow metal nuclei in a thin layer. Accordingly, there have been efforts to form metal interconnection layers using chemical vapor deposition techniques. In particular, there have been efforts to form aluminum interconnection layers using chemical vapor deposition techniques.
Aluminum layers formed using chemical vapor deposition techniques, however, may have an island-shape surface or otherwise rough surface morphology. Accordingly, it may be difficult to achieve uniform aluminum distribution in an opening such as a contact hole or via with a high aspect ratio, and it may be difficult to form long metal lines with uniform characteristics.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved methods and systems for forming metal layers for integrated circuit devices.
It is another object of the present invention to provide methods and systems for forming metal layers having improved surface characteristics.
It is still another object of the present invention to provide methods and systems for reducing the formation of voids in metal layers formed in high aspect ratio openings such as contact holes and vias.
It is yet another object of the present invention to provide methods and systems for forming metal layers having improved step coverage.
These and other objects are provided according to the present invention by monitoring a reflection index of the first conductive layer while forming the first conductive layer, and terminating formation of the first conductive layer when the reflection index of the first conductive layer reaches a predetermined value. The conductive layer thus formed has a relatively smooth and planar surface thus providing a conductive layer with uniform thickness. A smooth composite layer of a desired thickness can thus be provided by forming a plurality of these layers to provide a composite layer of the desired thickness which can be patterned to provide relatively long conductive lines with uniform thickness.
More particularly, a single conductive layer formed according to the present invention can have a thickness in the range of approximately 500 Angstroms to 1500 Angstroms, and the conductive layer can be a layer of aluminum. In addition, each of the conductive layers can be separated by a buffer layer wherein the buffer layer comprises a material different than that of the first conductive layer.
The buffer layer may have a thickness less than a thickness of the first conductive layer, and the buffer layer preferably has a thickness of no more than approximately 100 Angstroms. Moreover, the buffer layer can be a layer of a material such as copper (Cu), zinc (Zn), titanium (Ti), tungsten (W), tantalum (Ta), titanium nitride (Ti—N), tungsten nitride (Ti—N), tantalum nitride (Ta—N), titanium silicon nitride (Ti—Si—N), titanium boron nitride (Ti—B—N), titanium aluminum nitride (Ti—Al—N), tungsten boron nitride (W—B—N), tungsten silicon nitride (W—Si—N), tungsten aluminum nitride (W—Al—N), tantalum silicon nitride (Ta—Si—N), tantalum boron nitride (Ta—B—N), tantalum aluminum nitride (Ta—Al—N), and combinations thereof.
The methods and systems of the present invention can thus be used to provide relatively smooth and planar conductive aluminum layers by terminating formation of the individual aluminum layer when a reflection index thereof reaches a predetermined value. In addition, a desired thickness of a conductive layer can be achieved by forming a composite layer including a plurality of aluminum layers according to the present invention with each aluminum layer being separated by a thin conductive buffer layer.
The characteristics of a metal line formed using CVD techniques is dependent on the deposition conditions used. When the deposition precursor is a metalorganic compound, the thermal decomposition temperature of the deposition precursor varies according to the bonding characteristics of the deposition precursor. The CVD deposition rate is classified to two regions according to the deposition temperature. The deposition rate of a low temperature deposition region is largely determined based on the surface reaction of the substrate. On the other hand, the deposition rate of a high temperature deposition region is largely determined based on the gas flow rates. The deposition rates increase in proportion to increasing temperature in the low temperature deposition region (region of controlling the surface reaction), while the deposition rate is not significantly affected by the temperature in the high temperature deposition region (region of controlling delivering flow rate) thus maintaining almost a constant deposition rate.
Because relatively good step coverage is provided in the region of controlling the surface reaction when using chemical vapor deposition (CVD), chemical vapor deposition is used mainly in the region of controlling the surface reaction to overcome disadvantages of physical vapor deposition which may provide relatively poor step coverage. When using dimethyl amine alane as a deposition precursor, for example, the thermal decomposition temperature can be approximately 80° C. or less, and the temperature of the region of controlling the surface reaction can be approximately 200° C. or less.
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Keshaven Belur
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd
Smith Matthew
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