Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-12-26
2006-12-26
Pert, Evan (Department: 2826)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
Reexamination Certificate
active
07153772
ABSTRACT:
A method of self-aligned silicidation involves interruption of the silicidation process prior to complete reaction of the blanket material (e.g., metal) in regions directly overlying patterned and exposed other material (e.g., silicon). Diffusion of excess blanket material from over other regions (e.g., overlying insulators) is thus prevented. Control and uniformity are insured by use of conductive rapid thermal annealing in hot wall reactors, with massive heated plates closely spaced from the substrate surfaces. Interruption is particularly facilitated by forced cooling, preferably also by conductive thermal exchange with closely spaced, massive plates.
REFERENCES:
patent: 4521952 (1985-06-01), Riseman
patent: 4605947 (1986-08-01), Price et al.
patent: 4994402 (1991-02-01), Chiu
patent: 5032233 (1991-07-01), Yu et al.
patent: 5043300 (1991-08-01), Nulman
patent: 5084406 (1992-01-01), Rhodes et al.
patent: 5094977 (1992-03-01), Yu et al.
patent: 5147819 (1992-09-01), Yu et al.
patent: 5187122 (1993-02-01), Bonis
patent: 5196360 (1993-03-01), Doan et al.
patent: 5231056 (1993-07-01), Sandhu
patent: 5236865 (1993-08-01), Sandhu et al.
patent: 5278098 (1994-01-01), Wei et al.
patent: 5341016 (1994-08-01), Prall et al.
patent: 5378641 (1995-01-01), Cheffings
patent: 5389575 (1995-02-01), Chin et al.
patent: 5480814 (1996-01-01), Wuu et al.
patent: 5508212 (1996-04-01), Wang et al.
patent: 5656519 (1997-08-01), Mogami
patent: 5656546 (1997-08-01), Chen et al.
patent: 5756394 (1998-05-01), Manning
patent: 5856237 (1999-01-01), Ku
patent: 5888903 (1999-03-01), O'Brien et al.
patent: 5945350 (1999-08-01), Violette et al.
patent: 6177761 (2000-09-01), Manning
patent: 6147405 (2000-11-01), Hu
patent: 6183565 (2001-02-01), Granneman et al.
patent: 6277735 (2001-08-01), Matsubara
patent: 6372584 (2002-04-01), Yu
patent: 6455935 (2002-09-01), Hu
patent: 6524953 (2003-02-01), Hu
patent: 6743721 (2004-06-01), Lur et al.
patent: 60-10673 (1985-01-01), None
Lou, et al., “The Process Window of a-Si/Ti Bilayer Metallization for an Oxidation-Resistant and Self-Aligned TiSi2 Process,” IEEE Transactions on Electron Devices, vol. 39, No. 8, Aug. 1992, pp. 1835-1843.
Jeong Soo Byun, Hak Nam Kim et al., “Formation of a large grain sized TiN layer using TiN2,the epitaxial continuity at the Al/TiN interface . . .”, J. Appl. Phys. 78(3), Aug. 1, 1995, pp. 1719-1724.
Jeong Soo Byun, Chang Reol Kim et al., “TiN/TiSi2Formation Using TiNxLayer and Its Feasibilities in ULSI”, Jpn. J. Appl. Phys. vol. 35 (1995), pp. 982-986.
Jeong Soo Byun, “Epitaxial C49-TiSi2Formation on(100)Si Substrate Using TiNxand Its Electrical Characteristics as a Shallow Contact Metallization”, J. Electrochem. Soc., vol. 143, No. 6, Jun. 1996, pp. 1984-1991.
Jeong S. Byun, Kwan G. Rha et al., “Epitaxial TiSi2Growth on Si(100)From Reactive Sputtered TiNxand Subsequent Annealing”, Materials Research Soc. Proceedings, vol. 355, Pittsburgh, 1995, pp. 465-470.
Jeong Soo Byun, Jun Ki Kim et al., “W as a Bit Line Interconnection in Capacitor-Over-Bit-Line(COB)Structured Dynamic Random Access Memory(DRAM)and Feasible Diffusion Barrier Layer”, Jpn. J. Appl. Phys. vol. 35 (1996), pp. 1086-1089.
Van Houtum, H. et al., “TiSi2 strap formation by Ti-amorphous-Si reaction,” J. Vac. Sci. Technol. B 6(6), Nov./Dec. 1988, pp. 1734-1739.
Kuznetsov et al., “Continuity in development of ultra shallow junctions for 130-45 nm CMOS: the tool and annealing methods,” Abstract 11thIEEE, RTP 2003 Conference, Sep. 23-26, 2003, Charleston, USA.
Lauwers, et al., “Low temperature spike anneal for Ni-silicide formation,” Microelectronic Engineering 76, 303-310 (MAM2004, Brussels, Belgium, Mar. 7-10, 2004).
Pages, et al., “The effect of ramp rate—short process time and partial reactions on cobalt and nickel silicide formation,” Proceedings 205thECS Meeting, May 9-13, 2004, San Antonio TX, USA, p. 174-182.
Granneman Ernst H. A.
Kuznetsov Vladimir
Pages Xavier
van der Jeugd Cornelius A.
ASM International N.V.
Knobbe Martens Olson & Bear LLP
Pert Evan
LandOfFree
Methods of forming silicide films in semiconductor devices does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods of forming silicide films in semiconductor devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of forming silicide films in semiconductor devices will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3659049