Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2005-12-13
2005-12-13
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S734000, C438S750000, C438S700000
Reexamination Certificate
active
06974756
ABSTRACT:
A method of forming a shallow trench isolation is disclosed. An example method of forming a shallow trench isolation performs a planarization process for a substrate on which a hard mask and an insulation layer are formed, selectively etching the insulation layer on the edge of the substrate by using wet etch equipment, and performs a main etching process in the center region of the substrate.
REFERENCES:
patent: 5137843 (1992-08-01), Kim et al.
patent: 5358893 (1994-10-01), Yang et al.
patent: 5783097 (1998-07-01), Lo et al.
patent: 6162739 (2000-12-01), Sumnitsch et al.
patent: 6291315 (2001-09-01), Nakayama et al.
patent: 6340624 (2002-01-01), Doan et al.
patent: 6764920 (2004-07-01), Yang et al.
patent: 6777336 (2004-08-01), Lin et al.
patent: 2004/0110354 (2004-06-01), Natzle et al.
DongbuAnam Semiconductor Inc.
Fourson George
Hanley Flight & Zimmerman LLC
LandOfFree
Methods of forming shallow trench isolation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods of forming shallow trench isolation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of forming shallow trench isolation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3483200