Methods of forming semiconductor substrates using wafer...

Details Methods of forming semiconductor substrates using wafer... Methods of forming semiconductor substrates using wafer...

1999-03-26

2001-04-10

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

Thinning of semiconductor substrate

C438S465000, C438S976000, C257S640000, C257S701000

Reexamination Certificate

active

06214702

ABSTRACT:

RELATED APPLICATION
This application is related to Korean Application No. 98-10988, filed Mar. 30, 1998, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
This invention relates to integrated circuit device fabrication methods and devices formed thereby, and more particularly to semiconductor substrate fabrication methods and substrates formed thereby.
BACKGROUND OF THE INVENTION
Wafer bonding techniques may be utilized to form semiconductor-on-insulator (SOI) substrates. Such techniques typically involve steps to form an electrically insulating layer on a first wafer and then bond the first wafer to a second wafer with the electrically insulating layer disposed therebetween and acting as an adhesion layer. One of the wafers may then be polished using conventional techniques to form a semiconductor active layer that is electrically isolated from the other wafer by the electrically insulating layer. An example of such a bonding technique is described in U.S. Pat. No. 5,753,562 to Kim, entitled “Methods of Forming Semiconductor Devices in Substrates Having Inverted-Trench Isolation Regions Therein”, assigned to the present assignee, the disclosure of which is hereby incorporated herein by reference.
Recently, BPSG (borophosphosilicate glass) layers have been considered as adhesion material layers. When such layers are used in an SOI process, annealing steps may be performed at temperatures less than 850° C. to increase bond strength. However, during such annealing steps to increase bond strength, impurities and contaminants can out-diffuse from the BPSG layer and into the first and second wafers where they may adversely influence the electrical characteristics of devices subsequently formed therein.
Referring now to
FIG. 1
, a cross-sectional view of a conventional semiconductor substrate (e.g., SOI substrate) will be described. In particular, the substrate of
FIG. 1
includes a processing wafer
10
(wherein a variety of active semiconductor devices are to be formed), a handling wafer
12
, a BPSG layer
14
and a silicon nitride layer
13
. As will be understood by those skilled in the art, the BPSG layer
14
acts as an adhesion layer and the silicon nitride layer
13
acts as a diffusion barrier layer to inhibit direct transfer of boron and phosphorus impurities from the BPSG layer
14
to the processing wafer
10
during subsequent thermal treatment steps (e.g., annealing).
In order to increase the degree of bonding (i.e., bond strength) between the processing and handling wafers
10
and
12
, an annealing step is typically carried out at temperature of about 950° C. However, during such an annealing step, phosphorous and boron impurities may diffuse out from the ends of the BPSG layer
14
(as illustrated by the arrows in
FIG. 1
) and contaminate the bonded wafers
10
and
12
. When these contaminated wafers are then loaded into new manufacturing apparatus, the manufacturing apparatus and handling devices may also become contaminated with boron and phosphorous impurities.
To solve these contamination problems, attempts have been made to use adhesion materials other than BPSG. For example, undoped silicate glass (USG) has been considered as an alternative to BPSG. Unfortunately, USG typically does not provide a sufficiently strong bond between wafers. Attempts to increase the bond strength of USG have included increasing the annealing temperature, but such increases in annealing temperature can produce parasitic voids in the bond interface. Thus, notwithstanding the above described methods of bonding wafers and forming SOI substrates, there continues to be a need for improved wafer bonding methods which are more suitable for forming SOI substrates.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved methods of forming integrated circuit substrates.
It is another object of the present invention to provide methods of forming semiconductor-on-insulator substrates that have reduced susceptibility to contamination related defects.
These and other objects, advantages and features of the present invention are provided by methods of forming integrated circuit substrates that comprise the step of bonding a first semiconductor substrate to a second semiconductor substrate. The first semiconductor substrate has a first adhesion layer thereon extending opposite a first surface thereof and a first diffusion barrier layer extending between the first adhesion layer and the first surface. The second semiconductor substrate has a second adhesion layer thereon. The first diffusion barrier layer may comprise a silicon nitride layer formed using a low pressure chemical vapor deposition (LPCVD) technique with NH
3
and dichlorosilane (DCS). The first adhesion layer may also comprise a borophosphosilicate glass (BPSG) layer. The first diffusion barrier layer prevents impurities from within the first adhesion layer from diffusing directly into the first semiconductor substrate during subsequent thermal treatment steps (e.g., annealing). The second adhesion layer may also be formed of BPSG.
In order to increase the strength of the chemical bond between the first semiconductor substrate and the second semiconductor substrate, an annealing step should be carried out. The annealing step may be carried out in a nitrogen ambient for about 30 minutes at temperature of about 900° C. According to a preferred aspect of the present invention, a second diffusion barrier layer is then formed to encapsulate the bonded wafers and the adhesion layers and diffusion barrier layer therebetween. The second diffusion barrier layer prevents impurities from within the adhesion layers from out-diffusing (from the lateral edges of the adhesion layers) during the subsequent thermal treatment steps (e.g., annealing steps). The second diffusion barrier layer may comprise silicon nitride or silicon oxynitride.
An additional annealing step may be carried out to further improve the bond strength between the substrates. This annealing step may be carried out in a nitrogen ambient, for a duration of about 30 minutes and at temperature about 950° C. After this final annealing step, a second surface of the first semiconductor substrate may be polished (e.g., using CMP) to form an active semiconductor layer. Active semiconductor devices may then be formed in the active semiconductor layer.


REFERENCES:
patent: 4671846 (1987-06-01), Shimbo et al.
patent: 5366923 (1994-11-01), Beyer et al.
patent: 5665631 (1997-09-01), Lee et al.
patent: 5750000 (1998-05-01), Yonehara et al.
patent: 5753562 (1998-05-01), Kim
McNamara, J.M.; Raby, J.S.; Wafer Bonding Using Low Temperature Melting Glass. IEEE Proceeding of SOS/SOI Technology Workshop, 1988. p. 14.

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