Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2007-04-10
2007-04-10
Vinh, Lan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S231000, C438S706000, C438S714000
Reexamination Certificate
active
10625452
ABSTRACT:
Methods of forming a semiconductor device are provided by forming a gate pattern that includes a gate electrode on a substrate. Lightly doped impurity diffusion layers are formed in the substrate at both sides of the gate pattern. Spacers are formed on sidewalls of the gate pattern. The spacers having a bottom width. Impurity ions are implanted using the gate pattern and the spacer as a mask to form a heavily doped impurity diffusion layer in the substrate. The spacers are removed. A conformal etch stop layer is formed on the gate pattern and the substrate. The etch stop layer is formed to a thickness of at least the bottom width of the spacers.
REFERENCES:
patent: 6153455 (2000-11-01), Ling et al.
patent: 6207987 (2001-03-01), Tottori
patent: 6451704 (2002-09-01), Pradeep et al.
patent: 2001-244457 (2001-09-01), None
Notice to File Response to a Rejection dated Jun. 21, 2004 issued by the Korean Intellectual Property Office for Korean Application No. 2002-66087.
Hwang Byung-Jun
Kim Han-Soo
Koh Kwang-Ok
Kwak Kun-Ho
Myers Bigel & Sibley Sajovec, PA
Samsung Electronics Co,. Ltd.
Vinh Lan
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