Methods of forming semiconductor devices in substrates having in

Details Methods of forming semiconductor devices in substrates having in Methods of forming semiconductor devices in substrates having in

1996-12-13

1998-05-19

Niebling, John

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438435, 438459, 438221, 438296, 438977, H01L 2176

Patent

active

057535620

ABSTRACT:
Methods of forming semiconductor substrates having inverted-trench isolation regions therein include the steps of forming at least one trench in a semiconductor substrate at a first face thereof and then forming a stopping layer on the bottom of the trench. An etching or polishing step is then performed on a second face of the substrate which extends opposite the first face, until the stopping layer is exposed. Semiconductor devices are then formed in the remaining portions of the substrate extending adjacent sidewalls of the trench, at the polished second face. In particular, first and second trenches are preferably formed at a first face of a first semiconductor substrate and then respective first and second stopping layers comprising silicon nitride are formed on bottoms of the first and second trenches. First and second electrically insulating layers (e.g., SiO.sub.2) are then formed on the first and second stopping layers, to fill the first and second trenches. The electrically insulating layers are then polished using a chemical-mechanical polishing step to form a substantially planar surface to which a second substrate is preferably bonded. A second face of the first substrate, extending opposite the first face, is then polished until the stopping layers are exposed and a smooth semiconductor surface is defined extending between the first and second trenches. Semiconductor devices are then formed in the substrate, opposite the smooth semiconductor surface and between the insulation-filled trenches.

REFERENCES:
patent: 4851366 (1989-07-01), Blanchard
patent: 5618752 (1997-04-01), Gaul
patent: 5627106 (1997-05-01), Hsu
Haisma et al., Silicon-on-Insulator Wafer Bonding-Wafer Thinning Technological Evaluations, Japanses Journal of aplied Physics, vol. 28, #8, (1989), pp. 1433-1434, Apr. 10, 1989.

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