Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-06-13
2006-06-13
Nguyen, Ha Tran (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S964000, C438S686000, C438S398000
Reexamination Certificate
active
07060615
ABSTRACT:
A method of forming a roughened layer of platinum, including: a) providing a substrate within a reaction chamber; b) forming an adhesion layer over the substrate; c) flowing an oxidizing gas into the reaction chamber; d) flowing a platinum precursor into the reaction chamber and depositing platinum from the platinum precursor onto the adhesion layer in the presence of the oxidizing gas; and e) maintaining a temperature within the reaction chamber at from about 0° C. to less than 300° C. during the depositing.
REFERENCES:
patent: 3856709 (1974-12-01), Porta et al.
patent: 3975304 (1976-08-01), della Porta et al.
patent: 4341662 (1982-07-01), Pfefferle
patent: 4425261 (1984-01-01), Stenius et al.
patent: 4431750 (1984-02-01), McGinnis et al.
patent: 4714693 (1987-12-01), Targos
patent: 4719442 (1988-01-01), Bohara et al.
patent: 5053917 (1991-10-01), Miyasaka et al.
patent: 5208479 (1993-05-01), Mathews et al.
patent: 5320978 (1994-06-01), Hsu
patent: 5330700 (1994-07-01), Soukup et al.
patent: 5525570 (1996-06-01), Chakraborty et al.
patent: 5555486 (1996-09-01), Kingon et al.
patent: 5635420 (1997-06-01), Nishioka
patent: 5639685 (1997-06-01), Zahurak et al.
patent: 5763286 (1998-06-01), Figura et al.
patent: 5783716 (1998-07-01), Baum et al.
patent: 5796648 (1998-08-01), Kawakubo et al.
patent: 5874364 (1999-02-01), Nakabayashi et al.
patent: 5917213 (1999-06-01), Iyer et al.
patent: 5990559 (1999-11-01), Marsh
patent: 6010744 (2000-01-01), Buskirk et al.
patent: 6033953 (2000-03-01), Aoki et al.
patent: 6175129 (2001-01-01), Liu et al.
patent: 6232629 (2001-05-01), Nakamura
patent: 0 415 751 (1991-03-01), None
patent: 0 855 738 (1998-07-01), None
patent: 5-67730 (1992-03-01), None
patent: 9051079 (1997-02-01), None
patent: 9-082666 (1997-03-01), None
patent: H09-239891 (1997-12-01), None
patent: 10173149 (1998-06-01), None
patent: 10180098 (1998-07-01), None
patent: 8017939 (2003-06-01), None
Ju-Hong Kwan et al.; “Characterization of Pt Thin Films Deposited by Metallorganic Chemical Vapor Deposition for Ferroelectric Bottom Electrodes”; J. Electrochem. Soc., vol. 144, No. 8, Aug. 1997; pp. 2848-2854.
M. Ino et al.; “Rugged surface polycrystalline silicon film deposition and its application in a stacked dynamic random access memory capacitor electrode”; J. Vac. Technol. B 14(2), Mar./Apr. 1996; pp. 751-756.
Nasu, T. et al., “Study of Pt Bottom Electrodes Using High-Temperature Sputtering for Ferroelectric Memories with SrBi2Ta2O9(SBTO) Film”, Jpn. J. Appl. Phys. vol. 37, Part 1, No. 7 (Jul. 1998), pp. 4144-4148.
Micro)n Technology, Inc.
Nguyen Ha Tran
Wells St. John P.S.
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